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/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-evm-quad-port-eth-exp.dtso19 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
20 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
21 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
22 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
59 phys = <&cpsw0_phy_gmii_sel 4>;
H A Dk3-j721e-evm-quad-port-eth-exp.dtso21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
24 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
61 phys = <&cpsw0_phy_gmii_sel 4>;
H A Dk3-j721e-evm-gesi-exp-board.dtso21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
24 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
66 phys = <&cpsw0_phy_gmii_sel 4>;
131 J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */
132 J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */
133 J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */
134 J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */
135 J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt61 emif1: emif@4c000000 {
62 compatible = "ti,emif-4d";
73 emif: emif@4c000000 {
80 emif1: emif@4c000000 {
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra74x-p.dtsi15 emif1: emif@4c000000 {
/openbmc/linux/Documentation/devicetree/bindings/hwlock/
H A Dst,stm32-hwspinlock.yaml41 hwspinlock@4c000000 {
/openbmc/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dsata-uctl.txt28 uctl@118006c000000 {
40 interrupts = <2 4>; /* Bit: 2, level */
/openbmc/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021-achip.dtsi60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
77 soc@9c000000 {
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dpxa-usb.txt24 usb0: ohci@4c000000 {
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dk3-ringacc.yaml37 minItems: 4
46 minItems: 4
82 ringacc: ringacc@3c000000 {
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear320-evb.dts23 st,pinmux-mode = <4>;
83 fsmc: flash@4c000000 {
H A Dspear320.dtsi32 fsmc: flash@4c000000 {
H A Dspear320-hmi.dts23 st,pinmux-mode = <4>;
99 fsmc: flash@4c000000 {
254 ts,sample-time = <4>;
260 ts,settling = <4>;
/openbmc/linux/arch/sh/mm/
H A DKconfig12 On other systems (such as the SH-3 and 4) where an MMU exists,
35 The page size is not necessarily 4KB. Keep this in mind when
50 boards typically map RAM at 0C000000.
83 32-bits through the SH-4A PMB. If this is not set, legacy
155 bool "4kB"
175 This enables support for 64kB pages, possible on all SH-4
198 bool "4MB"
239 Since there's sill some aliasing issues on SH-4, this option will
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Damphion,vpu.yaml114 vpu: vpu@2c000000 {
125 interrupts = <0 472 4>;
133 interrupts = <0 473 4>;
141 interrupts = <0 474 4>;
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa27x.dtsi30 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
41 usb0: usb@4c000000 {
98 interrupts = <4>;
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6115-fxtec-pro1x.dts24 framebuffer0: framebuffer@5c000000 {
26 reg = <0x0 0x5c000000 0x0 (1080 * 2160 * 4)>;
29 stride = <(1080 * 4)>;
214 gpio-reserved-ranges = <0 4>, <14 4>;
H A Dsdm670-google-sargo.dts42 framebuffer@9c000000 {
44 reg = <0 0x9c000000 0 (1080 * 2220 * 4)>;
47 stride = <(1080 * 4)>;
129 framebuffer-region@9c000000 {
482 gpio-reserved-ranges = <0 4>, <81 4>;
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts75 interrupts = <0 85 4>;
90 interrupts = <0 86 4>,
91 <0 87 4>;
96 scu@2c000000 {
133 interrupts = <0 84 4>;
140 interrupts = <0 68 4>,
141 <0 69 4>;
187 arm,vexpress-sysreg,func = <1 4>;
205 arm,vexpress-sysreg,func = <4 0>;
221 interrupt-map = <0 0 &gic 0 36 4>,
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-opp-vesnin.dts30 flash_memory: region@5c000000 {
40 gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>;
/openbmc/openbmc/meta-facebook/meta-bletchley/recipes-bletchley/mdio-util/files/
H A Dmdio-util21 C45_READ_CMD=$((16#8C000000))
33 MDIO_DATA_REG=$((MDIO_CTRL_REG+4))
75 WR_DATA=$4
78 MDIO_DATA_REG=$((MDIO_CTRL_REG+4))
103 DEV_ADDR=$4
153 MDIO_DATA_REG=$((MDIO_CTRL_REG+4))
187 PHY_ADDR=$4
/openbmc/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts69 flash@1c000000 {
74 bank-width = <4>;
221 reg-io-width = <4>;
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
236 reg-io-width = <4>;
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
250 reg-io-width = <4>;
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls1088a.dtsi53 fsl_mc: fsl-mc@80c000000 {
75 num-cs = <4>;
83 bus-width = <4>;
116 num-lanes = <4>;
132 num-lanes = <4>;
157 interrupts = <0 133 4>;
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
159 plic: interrupt-controller@c000000 {
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2e.dtsi89 msm_ram: sram@c000000 {
144 reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
160 <0 0 0 4 &pcie_intc1 3>; /* INT D */

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