1496cdc82SSiddharth Vadapalli// SPDX-License-Identifier: GPL-2.0 2496cdc82SSiddharth Vadapalli/** 3496cdc82SSiddharth Vadapalli * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with 4496cdc82SSiddharth Vadapalli * J7200 board. 5496cdc82SSiddharth Vadapalli * 6496cdc82SSiddharth Vadapalli * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 7496cdc82SSiddharth Vadapalli */ 8496cdc82SSiddharth Vadapalli 9496cdc82SSiddharth Vadapalli/dts-v1/; 10496cdc82SSiddharth Vadapalli/plugin/; 11496cdc82SSiddharth Vadapalli 12496cdc82SSiddharth Vadapalli#include <dt-bindings/gpio/gpio.h> 13496cdc82SSiddharth Vadapalli 14496cdc82SSiddharth Vadapalli#include "k3-pinctrl.h" 15*8d08d7aaSJayesh Choudhary#include "k3-serdes.h" 16496cdc82SSiddharth Vadapalli 17496cdc82SSiddharth Vadapalli&{/} { 18496cdc82SSiddharth Vadapalli aliases { 19496cdc82SSiddharth Vadapalli ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 20496cdc82SSiddharth Vadapalli ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 21496cdc82SSiddharth Vadapalli ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; 22496cdc82SSiddharth Vadapalli ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; 23496cdc82SSiddharth Vadapalli }; 24496cdc82SSiddharth Vadapalli}; 25496cdc82SSiddharth Vadapalli 26496cdc82SSiddharth Vadapalli&cpsw0 { 27496cdc82SSiddharth Vadapalli status = "okay"; 28496cdc82SSiddharth Vadapalli}; 29496cdc82SSiddharth Vadapalli 30496cdc82SSiddharth Vadapalli&cpsw0_port1 { 31496cdc82SSiddharth Vadapalli status = "okay"; 32496cdc82SSiddharth Vadapalli phy-handle = <&cpsw5g_phy0>; 33496cdc82SSiddharth Vadapalli phy-mode = "qsgmii"; 34496cdc82SSiddharth Vadapalli mac-address = [00 00 00 00 00 00]; 35496cdc82SSiddharth Vadapalli phys = <&cpsw0_phy_gmii_sel 1>; 36496cdc82SSiddharth Vadapalli}; 37496cdc82SSiddharth Vadapalli 38496cdc82SSiddharth Vadapalli&cpsw0_port2 { 39496cdc82SSiddharth Vadapalli status = "okay"; 40496cdc82SSiddharth Vadapalli phy-handle = <&cpsw5g_phy1>; 41496cdc82SSiddharth Vadapalli phy-mode = "qsgmii"; 42496cdc82SSiddharth Vadapalli mac-address = [00 00 00 00 00 00]; 43496cdc82SSiddharth Vadapalli phys = <&cpsw0_phy_gmii_sel 2>; 44496cdc82SSiddharth Vadapalli}; 45496cdc82SSiddharth Vadapalli 46496cdc82SSiddharth Vadapalli&cpsw0_port3 { 47496cdc82SSiddharth Vadapalli status = "okay"; 48496cdc82SSiddharth Vadapalli phy-handle = <&cpsw5g_phy2>; 49496cdc82SSiddharth Vadapalli phy-mode = "qsgmii"; 50496cdc82SSiddharth Vadapalli mac-address = [00 00 00 00 00 00]; 51496cdc82SSiddharth Vadapalli phys = <&cpsw0_phy_gmii_sel 3>; 52496cdc82SSiddharth Vadapalli}; 53496cdc82SSiddharth Vadapalli 54496cdc82SSiddharth Vadapalli&cpsw0_port4 { 55496cdc82SSiddharth Vadapalli status = "okay"; 56496cdc82SSiddharth Vadapalli phy-handle = <&cpsw5g_phy3>; 57496cdc82SSiddharth Vadapalli phy-mode = "qsgmii"; 58496cdc82SSiddharth Vadapalli mac-address = [00 00 00 00 00 00]; 59496cdc82SSiddharth Vadapalli phys = <&cpsw0_phy_gmii_sel 4>; 60496cdc82SSiddharth Vadapalli}; 61496cdc82SSiddharth Vadapalli 62496cdc82SSiddharth Vadapalli&cpsw5g_mdio { 63496cdc82SSiddharth Vadapalli status = "okay"; 64496cdc82SSiddharth Vadapalli pinctrl-names = "default"; 65496cdc82SSiddharth Vadapalli pinctrl-0 = <&mdio0_pins_default>; 66496cdc82SSiddharth Vadapalli reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; 67496cdc82SSiddharth Vadapalli reset-post-delay-us = <120000>; 68496cdc82SSiddharth Vadapalli #address-cells = <1>; 69496cdc82SSiddharth Vadapalli #size-cells = <0>; 70496cdc82SSiddharth Vadapalli 71496cdc82SSiddharth Vadapalli cpsw5g_phy0: ethernet-phy@16 { 72496cdc82SSiddharth Vadapalli reg = <16>; 73496cdc82SSiddharth Vadapalli }; 74496cdc82SSiddharth Vadapalli cpsw5g_phy1: ethernet-phy@17 { 75496cdc82SSiddharth Vadapalli reg = <17>; 76496cdc82SSiddharth Vadapalli }; 77496cdc82SSiddharth Vadapalli cpsw5g_phy2: ethernet-phy@18 { 78496cdc82SSiddharth Vadapalli reg = <18>; 79496cdc82SSiddharth Vadapalli }; 80496cdc82SSiddharth Vadapalli cpsw5g_phy3: ethernet-phy@19 { 81496cdc82SSiddharth Vadapalli reg = <19>; 82496cdc82SSiddharth Vadapalli }; 83496cdc82SSiddharth Vadapalli}; 84496cdc82SSiddharth Vadapalli 85496cdc82SSiddharth Vadapalli&exp2 { 86496cdc82SSiddharth Vadapalli qsgmii-line-hog { 87496cdc82SSiddharth Vadapalli gpio-hog; 88496cdc82SSiddharth Vadapalli gpios = <16 GPIO_ACTIVE_HIGH>; 89496cdc82SSiddharth Vadapalli output-low; 90496cdc82SSiddharth Vadapalli line-name = "qsgmii-pwrdn-line"; 91496cdc82SSiddharth Vadapalli }; 92496cdc82SSiddharth Vadapalli}; 93496cdc82SSiddharth Vadapalli 94496cdc82SSiddharth Vadapalli&main_pmx0 { 95a4956811STony Lindgren mdio0_pins_default: mdio0-default-pins { 96496cdc82SSiddharth Vadapalli pinctrl-single,pins = < 97496cdc82SSiddharth Vadapalli J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ 98496cdc82SSiddharth Vadapalli J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ 99496cdc82SSiddharth Vadapalli >; 100496cdc82SSiddharth Vadapalli }; 101496cdc82SSiddharth Vadapalli}; 102