Home
last modified time | relevance | path

Searched +full:36 +full:- +full:bit (Results 1 – 25 of 1022) sorted by relevance

12345678910>>...41

/openbmc/linux/Documentation/core-api/
H A Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
[all …]
/openbmc/linux/drivers/crypto/cavium/cpt/
H A Dcpt_common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #define CPT_FLAG_SRIOV_ENABLED BIT(1)
21 #define CPT_FLAG_VF_DRIVER BIT(2)
22 #define CPT_FLAG_DEVICE_READY BIT(3)
24 #define cpt_sriov_enabled(cpt) ((cpt)->flags & CPT_FLAG_SRIOV_ENABLED)
25 #define cpt_vf_driver(cpt) ((cpt)->flags & CPT_FLAG_VF_DRIVER)
26 #define cpt_device_ready(cpt) ((cpt)->flags & CPT_FLAG_DEVICE_READY)
39 #define CPTX_PF_CONSTANTS(a) (0x0ll + ((u64)(a) << 36))
40 #define CPTX_PF_RESET(a) (0x100ll + ((u64)(a) << 36))
41 #define CPTX_PF_DIAG(a) (0x120ll + ((u64)(a) << 36))
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dapple,sart.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sven Peter <sven@svenpeter.dev>
20 and allows 36 bit of physical address space and filter entries with sizes
21 up to 24 bit.
23 SART2, first seen in A14 and M1, allows 36 bit of physical address space
24 and filter entry size up to 36 bit.
27 entry size to 42 bit.
32 - items:
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dsys_wildfire.c1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
H A Dsys_sable.c1 // SPDX-License-Identifier: GPL-2.0
9 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
58 * 0-7 (char at 536)
59 * 8-15 (char at 53a)
60 * 16-23 (char at 53c)
64 * Bit Meaning Kernel IRQ
65 *------------------------------------------
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_devcpu_gcb_miim_regs.h1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36))
10 #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36))
11 #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36))
13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_devcpu_gcb_miim_regs.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
9 #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36))
10 #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36))
11 #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36))
13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_devcpu_gcb_miim_regs.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
9 #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36))
10 #define MIIM_MII_CMD(gi) (0xcc + (gi * 36))
11 #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36))
13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_devcpu_gcb_miim_regs.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
9 #define MIIM_MII_STATUS(gi) (0x5c + (gi * 36))
10 #define MIIM_MII_CMD(gi) (0x64 + (gi * 36))
11 #define MIIM_MII_DATA(gi) (0x68 + (gi * 36))
13 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) ((x) ? BIT(3) : 0)
15 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) ((x) ? BIT(31) : 0)
20 #define MSCC_F_MII_CMD_MIIM_CMD_SCAN(x) ((x) ? BIT(0) : 0)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_devcpu_gcb_miim_regs.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
11 #define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36))
12 #define MIIM_MII_CMD(gi) (0xa8 + (gi * 36))
13 #define MIIM_MII_DATA(gi) (0xac + (gi * 36))
15 #define MSCC_F_MII_STATUS_MIIM_STAT_BUSY(x) (x ? BIT(3) : 0)
17 #define MSCC_F_MII_CMD_MIIM_CMD_VLD(x) (x ? BIT(31) : 0)
/openbmc/linux/arch/arm/include/asm/
H A Ddomain.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 * DOMAIN_IO - domain 2 includes all IO only
19 * DOMAIN_USER - domain 1 includes all user memory only
20 * DOMAIN_KERNEL - domain 0 includes all kernel memory only
22 * The domain numbering depends on whether we support 36 physical
23 * address for I/O or not. Addresses above the 32 bit boundary can
26 * but there may be systems with supersection support and no 36-bit
30 * 36-bit addressing and supersections are only available on
92 : "m" (current_thread_info()->cpu_domain)); in get_domain()
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_pci.c93 .platform_engine_mask = BIT(RCS0), \
108 .platform_engine_mask = BIT(RCS0), \
140 .platform_engine_mask = BIT(RCS0), \
184 .dma_mask_size = 36,
190 .dma_mask_size = 36,
197 .dma_mask_size = 36,
203 .platform_engine_mask = BIT(RCS0), \
207 .dma_mask_size = 36, \
231 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
239 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
32 * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
33 * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
[all …]
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_hx8353d.c1 // SPDX-License-Identifier: GPL-2.0+
22 par->fbtftops.reset(par); in init_display()
43 /* SLPOUT - Sleep out & booster on */ in init_display()
47 /* DISPON - Display On */ in init_display()
53 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, in init_display()
56 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, in init_display()
59 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62); in init_display()
76 #define my BIT(7)
77 #define mx BIT(6)
78 #define mv BIT(5)
[all …]
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pow.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * New, starting with SDK 1.7.0, cvmx-pow supports a number of
36 * enabled. For example, cvmx-pow will check for the following
38 * - Requesting a POW operation with an active tag switch in
40 * - Waiting for a tag switch to complete for an excessively
43 * - Illegal tag switches from NULL_NULL.
44 * - Illegal tag switches from NULL.
45 * - Illegal deschedule request.
[all …]
/openbmc/qemu/hw/intc/
H A Dpnv_xive2_regs.h4 * Copyright (c) 2019-2022, IBM Corporation.
7 * COPYING file in the top-level directory.
66 #define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */
67 #define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */
69 #define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38) /* 0 if bit[25]=1 */
70 #define CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT PPC_BIT(39) /* 0 if bit[25]=1 */
72 /* Interrupt Controller Base Address Register - 512 pages (32M) */
81 /* Thread Management Base Address Register - 4 pages */
97 /* 0 (16M) - 16 (16T) */
116 #define CQ_TAR_ESB 0 /* 0 - 15 */
[all …]
H A Dgicv3_internal.h2 * ARM GICv3 support - internal interfaces
65 /* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */
149 FIELD(GICR_PENDBASER, PHYADDR, 16, 36)
164 FIELD(GICR_VPENDBASER, PHYADDR, 16, 36)
244 /* Note that EOI shares with the top bit of the pINTID field */
289 FIELD(GITS_BASER, PHYADDR, 12, 36)
323 FIELD(GITS_TYPER, CIL, 36, 1)
376 #define ICID_MASK ((1U << ICID_LENGTH) - 1)
380 #define RDBASE_PROCNUM_MASK ((1ULL << RDBASE_PROCNUM_LENGTH) - 1)
389 #define EVENTID_MASK ((1ULL << 32) - 1)
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen2-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
22 #define CPG_FRQCRB_KICK BIT(31)
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dnmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define MCCK_CODE_SYSTEM_DAMAGE BIT(63)
23 #define MCCK_CODE_EXT_DAMAGE BIT(63 - 5)
24 #define MCCK_CODE_CP BIT(63 - 9)
25 #define MCCK_CODE_STG_ERROR BIT(63 - 16)
26 #define MCCK_CODE_STG_KEY_ERROR BIT(63 - 18)
27 #define MCCK_CODE_STG_DEGRAD BIT(63 - 19)
28 #define MCCK_CODE_PSW_MWP_VALID BIT(63 - 20)
29 #define MCCK_CODE_PSW_IA_VALID BIT(63 - 23)
30 #define MCCK_CODE_STG_FAIL_ADDR BIT(63 - 24)
[all …]
/openbmc/linux/arch/ia64/kernel/
H A Dpatch.c1 // SPDX-License-Identifier: GPL-2.0
3 * Instruction-patching support.
5 * Copyright (C) 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
19 * The 64-bit value in a "movl reg=value" is scattered between the two words of the bundle
32 u64 *p = (u64 *) (insn_addr & -16); /* mask out slot number */ in get_imm64()
40 ((p[1] & 0x000007f000000000UL) >> 36); /*G*/ in get_imm64()
47 u64 m0, m1, v0, v1, b0, b1, *b = (u64 *) (insn_addr & -16); in ia64_patch()
48 # define insn_mask ((1UL << 41) - 1) in ia64_patch()
52 shift = 5 + 41 * (insn_addr % 16); /* 5 bits of template, then 3 x 41-bit instructions */ in ia64_patch()
[all …]
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-connectivity/samba/samba/
H A D0007-Deleted-settiong-of-python-to-fix-the-install-confli.patch7 …file /usr/bin/samba-tool conflicts between attempted installs of samba-4.14.14-r0.core2_64 and lib…
8 …file /usr/sbin/samba-gpupdate conflicts between attempted installs of samba-4.14.14-r0.core2_64 an…
9 …nsupdate conflicts between attempted installs of samba-4.14.14-r0.core2_64 and lib32-samba-4.14.14…
10 …grade_db conflicts between attempted installs of samba-4.14.14-r0.core2_64 and lib32-samba-4.14.14…
11 …amba_kcc conflicts between attempted installs of samba-4.14.14-r0.core2_64 and lib32-samba-4.14.14…
12 …pnupdate conflicts between attempted installs of samba-4.14.14-r0.core2_64 and lib32-samba-4.14.14…
13 …gradedns conflicts between attempted installs of samba-4.14.14-r0.core2_64 and lib32-samba-4.14.14…
15 The conflict is because there is a difference between of lib32-samba-* and samba-* as the followin…
16 64bit:
17 sys.path.insert(0, "/usr/lib64/python3.10/site-packages")
[all …]
/openbmc/linux/include/scsi/
H A Dsrp.h14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
107 * having the 20-byte structure padded to 24 bytes on 64-bit architectures.
143 * struct srp_login_req_rdma - RDMA/CM login parameters.
145 * RDMA/CM over InfiniBand can only carry 92 - 36 = 56 bytes of private
172 * bytes on 64-bit architectures.
252 * The SRP spec defines the size of the RSP structure to be 36 bytes,
254 * 64-bit architectures.
288 * 36 bytes, so it needs to be packed to avoid having it padded to 40 bytes
289 * on 64-bit architectures.
/openbmc/linux/Documentation/fb/
H A Dcmap_xfbdev.rst7 - example of relevant structures in fbdev as used for a 3-bit grayscale cmap::
20 info->cmap.red[i] = (((2*i)+1)*(0xFFFF))/16;
21 memcpy(info->cmap.green, info->cmap.red, sizeof(u16)*8);
22 memcpy(info->cmap.blue, info->cmap.red, sizeof(u16)*8);
24 - X11 apps do something like the following when trying to use grayscale::
29 sprintf(colorspec, "rgb:%x/%x/%x", i*36,i*36,i*36);
41 xc-011010/programs/Xserver/dix/colormap.c::
45 dr = (long) pent->co.local.red - prgb->red;
46 dg = (long) pent->co.local.green - prgb->green;
47 db = (long) pent->co.local.blue - prgb->blue;
[all …]
/openbmc/linux/arch/alpha/include/uapi/asm/
H A Dauxvec.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
12 value is -1, then the cache doesn't exist. Otherwise:
14 bit 0-3: Cache set-associativity; 0 means fully associative.
15 bit 4-7: Log2 of cacheline size.
16 bit 8-31: Size of the entire cache >> 8.
17 bit 32-63: Reserved.
22 #define AT_L2_CACHESHAPE 36
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-tao3530.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
26 cpu0-supply = <&vcc>;
37 compatible = "regulator-fixed";
38 regulator-name = "hsusb2_vbus";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
42 startup-delay-us = <70000>;
46 hsusb2_phy: hsusb2-phy-pins {
[all …]

12345678910>>...41