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/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tmu.dtsi19 hysteresis = <1000>; /* millicelsius */
24 hysteresis = <1000>; /* millicelsius */
29 hysteresis = <1000>; /* millicelsius */
34 hysteresis = <1000>; /* millicelsius */
39 hysteresis = <1000>; /* millicelsius */
44 hysteresis = <1000>; /* millicelsius */
49 hysteresis = <1000>; /* millicelsius */
56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dclock.c151 /* 158MHz / 1 = 158MHz */ in init_clk_usdhc()
160 /* 158MHz / 1 = 158MHz */ in init_clk_usdhc()
282 * A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on), in clock_init()
284 * A7 side: SPLL PFD0 (scs selected, 413Mhz), in clock_init()
285 * APLL PFD0 (352Mhz), DDRCLK, all NIC clocks in clock_init()
286 * A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz, in clock_init()
287 * IP BUS (NIC1_BUS) = 58.6Mhz in clock_init()
303 /* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */ in clock_init()
334 printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000); in do_mx7_showclocks()
337 printf("PLL_A7_APLL %8d MHz\n", freq / 1000000); in do_mx7_showclocks()
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
55 [0x0] = 666 * 1000 * 1000,
56 [0x2] = 800 * 1000 * 1000,
57 [0x3] = 800 * 1000 * 1000,
58 [0x4] = 1066 * 1000 * 1000,
59 [0x5] = 1066 * 1000 * 1000,
60 [0x6] = 1200 * 1000 * 1000,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.c68 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
70 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
71 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
72 …SMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
73 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x09 ///< Set display phy clock frequency in MHZ …
74 …ine VBIOSSMC_MSG_GetFclkFrequency 0x0A ///< Get FCLK frequency, return frequemcy in MHZ
83 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
84 #define VBIOSSMC_MSG_GetDtbclkFreq 0x14 ///< Get DPREF clock frequency. Return in MHZ
85 …15 ///< Inform PMFW to turn on/off DTB clock arg = 1, turn DTB clock on 600MHz/ arg = 0 turn DTB c…
109 if (delay_us >= 1000) in dcn316_smu_wait_for_response()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.c83 #define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
85 #define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
86 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
87 …SMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
88 #define VBIOSSMC_MSG_GetDtbclkFreq 0x09 ///< Get display dtb clock frequency in MHZ …
89 …BIOSSMC_MSG_SetDtbClk 0x0A ///< Set dtb clock frequency, return frequemcy in MHZ
91 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0x0C ///< To ask PMFW turn off TMDP 48MHz refclk …
98 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
122 if (delay_us >= 1000) in dcn315_smu_wait_for_response()
123 msleep(delay_us/1000); in dcn315_smu_wait_for_response()
[all …]
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c126 /* Set APLL to 1000MHz */ in board_clock_init()
149 * Set dividers for MOUTcore = 1000 MHz in board_clock_init()
150 * coreout = MOUT / (ratio + 1) = 1000 MHz (0) in board_clock_init()
151 * corem0 = armclk / (ratio + 1) = 333 MHz (2) in board_clock_init()
152 * corem1 = armclk / (ratio + 1) = 166 MHz (5) in board_clock_init()
153 * periph = armclk / (ratio + 1) = 1000 MHz (0) in board_clock_init()
154 * atbout = MOUT / (ratio + 1) = 200 MHz (4) in board_clock_init()
155 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) in board_clock_init()
156 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) in board_clock_init()
157 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) in board_clock_init()
[all …]
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_mipi_dsi_common.c17 #define MHZ (1000 * 1000) macro
18 #define FIN_HZ (24 * MHZ)
20 #define DFIN_PLL_MIN_HZ (6 * MHZ)
21 #define DFIN_PLL_MAX_HZ (12 * MHZ)
23 #define DFVCO_MIN_HZ (500 * MHZ)
24 #define DFVCO_MAX_HZ (1000 * MHZ)
109 delay_val = MHZ / dsim->dsim_config->esc_clk; in exynos_mipi_dsi_wr_data()
238 sw_timeout = 1000; in exynos_mipi_dsi_pll_on()
267 * ~ 99.99 MHz 0000 in exynos_mipi_dsi_change_pll()
268 * 100 ~ 119.99 MHz 0001 in exynos_mipi_dsi_change_pll()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c694 pll_settings->reference_freq * 1000, in calculate_ss()
983 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); in dcn31_program_pix_clk()
1119 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
1120 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
1121 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
1122 {89910, 90000, 90000, 1000, 1001}, //90Mhz -> 89.91
1123 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87
1124 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
1125 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83
1126 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527
[all …]
/openbmc/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
92 #define SLEEP_FREQ (800 * 1000)
103 unsigned long refresh; /* DRAM refresh counter * 1000 */
125 {0, L0, 1000*1000},
126 {0, L1, 800*1000},
127 {0, L2, 400*1000},
128 {0, L3, 200*1000},
129 {0, L4, 100*1000},
175 /* L0 : [1000/200/100][166/83][133/66][200/200] */
[all …]
H A Dpmac32-cpufreq.c369 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_target()
429 ppc_proc_freq = cur_freq * 1000ul; in pmac_cpufreq_resume()
502 * frequency, it claims it to be around 84Mhz on some models while in pmac_cpufreq_init_MacRISC3()
503 * it appears to be approx. 101Mhz on all. Let's hack around here... in pmac_cpufreq_init_MacRISC3()
529 low_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
538 hi_freq = (*value) / 1000; in pmac_cpufreq_init_MacRISC3()
586 low_freq = (*value) / 1000; in pmac_cpufreq_init_750FX()
605 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
606 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
607 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
[all …]
H A Dpxa3xx-cpufreq.c88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
119 table[i].frequency = freqs[i].cpufreq_mhz * 1000; in setup_freqs_table()
[all …]
H A Delanfreq.c45 {1000, 0x02, 0x18},
56 {0, 0, 1000},
72 * at the moment. Frequencies from 1 to 33 MHz are generated
73 * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
74 * and have the rest of the chip running with 33 MHz.
89 /* Are we in CPU clock multiplied mode (66/99 MHz)? */ in elanfreq_get_cpu_frequency()
97 /* 33 MHz is not 32 MHz... */ in elanfreq_get_cpu_frequency()
101 return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000; in elanfreq_get_cpu_frequency()
117 * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency) in elanfreq_target()
124 udelay(1000); /* buffers have cleaned up */ in elanfreq_target()
[all …]
H A Dspeedstep-centrino.c83 frequency/voltage operating point; frequency in MHz, volts in mV.
85 #define OP(mhz, mv) \ argument
87 .frequency = (mhz) * 1000, \
88 .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
98 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
107 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
113 OP(1000, 1004),
123 OP(1000, 1164),
135 OP(1000, 1100),
146 OP(1000, 1292),
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_afmt.c35 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
36 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
37 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
38 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
39 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
40 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
41 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
42 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
43 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
44 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
[all …]
/openbmc/linux/arch/arm/mach-s3c/
H A Dcpu.h45 #ifndef MHZ
46 #define MHZ (1000*1000) macro
49 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ram.c46 debug("DDR: mem_speed (%d MHz), RCC %d MHz\n", in stm32mp1_ddr_clk_enable()
47 mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); in stm32mp1_ddr_clk_enable()
49 ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000); in stm32mp1_ddr_clk_enable()
50 if (ddr_clk > (mem_speed * 1000 * 100)) { in stm32mp1_ddr_clk_enable()
51 pr_err("DDR expected freq %d MHz, current is %d MHz\n", in stm32mp1_ddr_clk_enable()
52 mem_speed, (u32)(ddrphy_clk / 1000 / 1000)); in stm32mp1_ddr_clk_enable()
/openbmc/u-boot/drivers/timer/
H A Dtsc_timer.c51 crystal_freq = tsc_info.ecx / 1000; in native_calibrate_tsc()
59 crystal_freq = 24000; /* 24.0 MHz */ in native_calibrate_tsc()
62 crystal_freq = 25000; /* 25.0 MHz */ in native_calibrate_tsc()
65 crystal_freq = 19200; /* 19.2 MHz */ in native_calibrate_tsc()
72 return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000; in native_calibrate_tsc()
97 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
145 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
183 res = freq * ratio / 1000; in cpu_mhz_from_msr()
184 debug("TSC runs at %lu MHz\n", res); in cpu_mhz_from_msr()
196 * - the PIT is running at roughly 1.19MHz
[all …]
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf52x2/
H A Dcpu.c31 udelay(1000); in do_reset()
45 " CPU CLK %s MHz BUS CLK %s MHz\n", in print_cpuinfo()
85 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); in watchdog_init()
129 printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", in print_cpuinfo()
133 " (PIN: 0x%x) rev. %hu, at %s MHz\n", in print_cpuinfo()
180 udelay(1000); in do_reset()
251 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); in watchdog_init()
268 udelay(1000); in do_reset()
281 printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", in print_cpuinfo()
321 (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); in watchdog_init()
[all …]
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi.c31 #define MHZ(v) ((u32)((v) * 1000000U)) macro
102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/openbmc/linux/tools/testing/selftests/intel_pstate/
H A Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
60 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
80 # MAIN (ALL UNITS IN MHZ)
90 min_freq=$(($_min_freq / 1000))
92 max_freq=$(($_max_freq / 1000))
98 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c484 ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
486 ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
488 ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
490 ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
500 ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
502 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
504 ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
506 ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
545 static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) in pp_rv_set_hard_min_fclk_by_freq() argument
550 amdgpu_dpm_set_hard_min_fclk_by_freq(adev, mhz); in pp_rv_set_hard_min_fclk_by_freq()
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c35 #define OSC_HZ (24 * 1000 * 1000)
36 #define APLL_L_HZ (800 * 1000 * 1000)
37 #define APLL_B_HZ (816 * 1000 * 1000)
38 #define GPLL_HZ (576 * 1000 * 1000)
39 #define CPLL_HZ (400 * 1000 * 1000)
93 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; in rkclk_set_pll()
205 const ulong MHz = 1000000; in rk3368_mmc_find_best_rate_and_parent() local
212 { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz } in rk3368_mmc_find_best_rate_and_parent()
285 const ulong MHz = 1000000; in rk3368_ddr_set_clk() local
288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk()
[all …]
/openbmc/linux/tools/power/cpupower/utils/helpers/
H A Dmisc.c236 else if (speed > 1000) in print_speed()
237 printf("%u.%03u MHz", ((unsigned int)speed / 1000), in print_speed()
238 (unsigned int)(speed % 1000)); in print_speed()
249 tmp = speed % 1000; in print_speed()
251 speed += 1000; in print_speed()
252 printf("%u MHz", ((unsigned int)speed / 1000)); in print_speed()
253 } else if (speed > 1000) { in print_speed()
257 printf("%u.%01u MHz", ((unsigned int)speed / 1000), in print_speed()
258 ((unsigned int)(speed % 1000) / 100)); in print_speed()

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