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/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
H A Dpci-sh7780.c24 # define PCICR_ENDIANNESS 0
31 .start = 0x1000,
35 .name = "PCI MEM 0",
36 .start = 0xfd000000,
37 .end = 0xfd000000 + SZ_16M - 1,
41 .start = 0x10000000,
42 .end = 0x10000000 + SZ_64M - 1,
49 .start = 0xc0000000,
50 .end = 0xc0000000 + SZ_512M - 1,
59 .io_offset = 0,
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H A Dpcie-sh7786.h11 /* PCIe bus-0(x4) on SH7786 */ // Rev1.171
12 #define SH4A_PCIE_SPW_BASE 0xFE000000 /* spw config address for controller 0 */
13 #define SH4A_PCIE_SPW_BASE1 0xFE200000 /* spw config address for controller 1 (Rev1.14)*/
14 #define SH4A_PCIE_SPW_BASE2 0xFCC00000 /* spw config address for controller 2 (Rev1.171)*/
15 #define SH4A_PCIE_SPW_BASE_LEN 0x00080000
17 #define SH4A_PCI_CNFG_BASE 0xFE040000 /* pci config address for controller 0 */
18 #define SH4A_PCI_CNFG_BASE1 0xFE240000 /* pci config address for controller 1 (Rev1.14)*/
19 #define SH4A_PCI_CNFG_BASE2 0xFCC40000 /* pci config address for controller 2 (Rev1.171)*/
20 #define SH4A_PCI_CNFG_BASE_LEN 0x00040000
22 #define SH4A_PCIPIO_ADDR_OFFSET 0x000001c0 /* offset to pci config_address */
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/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7785.h12 #define CCR_CACHE_INIT 0x0000090b
15 #define TRA 0xFF000020
16 #define EXPEVT 0xFF000024
17 #define INTEVT 0xFF000028
20 #define CCR 0xFF00001C
21 #define QACR0 0xFF000038
22 #define QACR1 0xFF00003C
23 #define RAMCR 0xFF000074
27 #define WDTST 0xFFCC0000
28 #define WDTCSR 0xFFCC0004
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H A Dcpu_sh7780.h11 #define CCR_CACHE_INIT 0x0000090b
14 #define TRA 0xFF000020
15 #define EXPEVT 0xFF000024
16 #define INTEVT 0xFF000028
19 #define PTEH 0xFF000000
20 #define PTEL 0xFF000004
21 #define TTB 0xFF000008
22 #define TEA 0xFF00000C
23 #define MMUCR 0xFF000010
24 #define PASCR 0xFF000070
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/openbmc/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop2.yaml48 - description: Pixel clock for video port 0.
69 port@0:
111 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
128 #size-cells = <0>;
129 vp0: port@0 {
130 reg = <0>;
132 #size-cells = <0>;
137 #size-cells = <0>;
142 #size-cells = <0>;
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x.dtsi50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
65 reg = <0x0 0x100>;
74 reg = <0x0 0x200>;
83 reg = <0x0 0x300>;
90 cpu0_opp_table: opp-table-0 {
140 arm,smc-id = <0x82000010>;
143 #size-cells = <0>;
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