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Searched +full:0 +full:xfc800000 (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/configs/
H A Dintegratorcp_cm920t_defconfig3 CONFIG_SYS_TEXT_BASE=0x01000000
8 …tdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
H A Dintegratorcp_cm1136_defconfig3 CONFIG_SYS_TEXT_BASE=0x01000000
8 …tdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
H A Dintegratorcp_cm946es_defconfig3 CONFIG_SYS_TEXT_BASE=0x01000000
8 …tdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
H A Dintegratorcp_cm926ejs_defconfig3 CONFIG_SYS_TEXT_BASE=0x01000000
8 …tdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
/openbmc/u-boot/arch/arm/include/asm/arch-spear/
H A Dhardware.h10 #define CONFIG_SYS_USBD_BASE 0xE1100000
11 #define CONFIG_SYS_PLUG_BASE 0xE1200000
12 #define CONFIG_SYS_FIFO_BASE 0xE1000800
13 #define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
14 #define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000
15 #define CONFIG_SYS_SMI_BASE 0xFC000000
16 #define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
17 #define CONFIG_SPEAR_TIMERBASE 0xFC800000
18 #define CONFIG_SPEAR_MISCBASE 0xFCA80000
19 #define CONFIG_SPEAR_ETHBASE 0xE0800000
[all …]
/openbmc/linux/arch/arm/mach-spear/
H A Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,sp804.yaml93 reg = <0xfc800000 0x1000>;
94 interrupts = <0 0 4>, <0 1 4>;
/openbmc/linux/arch/sh/drivers/pci/
H A Dpcie-sh7786.c44 .name = "PCIe0 MEM 0",
45 .start = 0xfd000000,
46 .end = 0xfd000000 + SZ_8M - 1,
50 .start = 0xc0000000,
51 .end = 0xc0000000 + SZ_512M - 1,
55 .start = 0x10000000,
56 .end = 0x10000000 + SZ_64M - 1,
60 .start = 0xfe100000,
61 .end = 0xfe100000 + SZ_1M - 1,
68 .name = "PCIe1 MEM 0",
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x.dtsi50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
65 reg = <0x0 0x100>;
74 reg = <0x0 0x200>;
83 reg = <0x0 0x300>;
90 cpu0_opp_table: opp-table-0 {
140 arm,smc-id = <0x82000010>;
143 #size-cells = <0>;
[all …]
H A Drk3588s.dtsi23 #size-cells = <0>;
58 cpu_l0: cpu@0 {
61 reg = <0x0>;
82 reg = <0x100>;
101 reg = <0x200>;
120 reg = <0x300>;
139 reg = <0x400>;
160 reg = <0x500>;
179 reg = <0x600>;
200 reg = <0x700>;
[all …]
/openbmc/linux/drivers/accel/habanalabs/goya/
H A Dgoya_security.c22 while (pb_addr & 0xFFF) { in goya_pb_set_block()
23 WREG32(pb_addr, 0); in goya_pb_set_block()
34 u64 mmMME_SBB_POWER_ECO1 = 0xDFF60, in goya_init_mme_protection_bits()
35 mmMME_SBB_POWER_ECO2 = 0xDFF64; in goya_init_mme_protection_bits()
67 pb_addr = (mmMME_DUMMY & ~0xFFF) + PROT_BITS_OFFS; in goya_init_mme_protection_bits()
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]