Lines Matching +full:0 +full:xfc800000
23 #size-cells = <0>;
58 cpu_l0: cpu@0 {
61 reg = <0x0>;
82 reg = <0x100>;
101 reg = <0x200>;
120 reg = <0x300>;
139 reg = <0x400>;
160 reg = <0x500>;
179 reg = <0x600>;
200 reg = <0x700>;
221 arm,psci-suspend-param = <0x0010000>;
326 arm,smc-id = <0x82000010>;
329 #size-cells = <0>;
332 reg = <0x14>;
337 reg = <0x16>;
358 spll: clock-0 {
362 #clock-cells = <0>;
367 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
368 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
369 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
370 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
371 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
379 #clock-cells = <0>;
386 #clock-cells = <0>;
391 reg = <0x0 0x0010f000 0x0 0x100>;
392 ranges = <0 0x0 0x0010f000 0x100>;
396 scmi_shmem: sram@0 {
398 reg = <0x0 0x100>;
404 reg = <0x0 0xfc800000 0x0 0x40000>;
405 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
415 reg = <0x0 0xfc840000 0x0 0x40000>;
416 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
426 reg = <0x0 0xfc880000 0x0 0x40000>;
427 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
437 reg = <0x0 0xfc8c0000 0x0 0x40000>;
438 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
448 reg = <0x0 0xfd58c000 0x0 0x1000>;
453 reg = <0x0 0xfd5b0000 0x0 0x1000>;
458 reg = <0x0 0xfd5bc000 0x0 0x100>;
463 reg = <0x0 0xfd5c4000 0x0 0x100>;
468 reg = <0x0 0xfd5d8000 0x0 0x4000>;
474 reg = <0x8000 0x10>;
475 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
481 #clock-cells = <0>;
485 #phy-cells = <0>;
493 reg = <0x0 0xfd5dc000 0x0 0x4000>;
499 reg = <0xc000 0x10>;
500 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
506 #clock-cells = <0>;
510 #phy-cells = <0>;
518 reg = <0x0 0xfd5f0000 0x0 0x10000>;
523 reg = <0x0 0xfd600000 0x0 0x100000>;
524 ranges = <0x0 0x0 0xfd600000 0x100000>;
531 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
559 reg = <0x0 0xfd880000 0x0 0x1000>;
560 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
563 pinctrl-0 = <&i2c0m0_xfer>;
566 #size-cells = <0>;
572 reg = <0x0 0xfd890000 0x0 0x100>;
573 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
578 pinctrl-0 = <&uart0m1_xfer>;
587 reg = <0x0 0xfd8b0000 0x0 0x10>;
590 pinctrl-0 = <&pwm0m0_pins>;
598 reg = <0x0 0xfd8b0010 0x0 0x10>;
601 pinctrl-0 = <&pwm1m0_pins>;
609 reg = <0x0 0xfd8b0020 0x0 0x10>;
612 pinctrl-0 = <&pwm2m0_pins>;
620 reg = <0x0 0xfd8b0030 0x0 0x10>;
623 pinctrl-0 = <&pwm3m0_pins>;
631 reg = <0x0 0xfd8d8000 0x0 0x400>;
637 #size-cells = <0>;
643 #power-domain-cells = <0>;
645 #size-cells = <0>;
656 #power-domain-cells = <0>;
658 #size-cells = <0>;
666 #power-domain-cells = <0>;
674 #power-domain-cells = <0>;
688 #power-domain-cells = <0>;
694 #size-cells = <0>;
695 #power-domain-cells = <0>;
705 #power-domain-cells = <0>;
714 #power-domain-cells = <0>;
724 #size-cells = <0>;
725 #power-domain-cells = <0>;
736 #power-domain-cells = <0>;
770 #size-cells = <0>;
771 #power-domain-cells = <0>;
780 #power-domain-cells = <0>;
789 #power-domain-cells = <0>;
797 #power-domain-cells = <0>;
804 #power-domain-cells = <0>;
815 #size-cells = <0>;
816 #power-domain-cells = <0>;
828 #power-domain-cells = <0>;
842 #power-domain-cells = <0>;
857 #size-cells = <0>;
858 #power-domain-cells = <0>;
868 #power-domain-cells = <0>;
879 #power-domain-cells = <0>;
887 #power-domain-cells = <0>;
903 #power-domain-cells = <0>;
910 #power-domain-cells = <0>;
917 #power-domain-cells = <0>;
924 #power-domain-cells = <0>;
930 #power-domain-cells = <0>;
935 #power-domain-cells = <0>;
942 reg = <0x0 0xfddc0000 0x0 0x1000>;
943 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
948 dmas = <&dmac2 0>;
953 #sound-dai-cells = <0>;
959 reg = <0x0 0xfddf0000 0x0 0x1000>;
960 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
970 #sound-dai-cells = <0>;
976 reg = <0x0 0xfddfc000 0x0 0x1000>;
977 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
987 #sound-dai-cells = <0>;
993 reg = <0x0 0xfdf35000 0x0 0x20>;
998 reg = <0x0 0xfdf35200 0x0 0x20>;
1003 reg = <0x0 0xfdf35400 0x0 0x20>;
1008 reg = <0x0 0xfdf35600 0x0 0x20>;
1013 reg = <0x0 0xfdf36000 0x0 0x20>;
1018 reg = <0x0 0xfdf39000 0x0 0x20>;
1023 reg = <0x0 0xfdf3d800 0x0 0x20>;
1028 reg = <0x0 0xfdf3e000 0x0 0x20>;
1033 reg = <0x0 0xfdf3e200 0x0 0x20>;
1038 reg = <0x0 0xfdf3e400 0x0 0x20>;
1043 reg = <0x0 0xfdf3e600 0x0 0x20>;
1048 reg = <0x0 0xfdf40000 0x0 0x20>;
1053 reg = <0x0 0xfdf40200 0x0 0x20>;
1058 reg = <0x0 0xfdf40400 0x0 0x20>;
1063 reg = <0x0 0xfdf40500 0x0 0x20>;
1068 reg = <0x0 0xfdf40600 0x0 0x20>;
1073 reg = <0x0 0xfdf40800 0x0 0x20>;
1078 reg = <0x0 0xfdf41000 0x0 0x20>;
1083 reg = <0x0 0xfdf41100 0x0 0x20>;
1088 reg = <0x0 0xfdf60000 0x0 0x20>;
1093 reg = <0x0 0xfdf60200 0x0 0x20>;
1098 reg = <0x0 0xfdf60400 0x0 0x20>;
1103 reg = <0x0 0xfdf61000 0x0 0x20>;
1108 reg = <0x0 0xfdf61200 0x0 0x20>;
1113 reg = <0x0 0xfdf61400 0x0 0x20>;
1118 reg = <0x0 0xfdf62000 0x0 0x20>;
1123 reg = <0x0 0xfdf63000 0x0 0x20>;
1128 reg = <0x0 0xfdf64000 0x0 0x20>;
1133 reg = <0x0 0xfdf66000 0x0 0x20>;
1138 reg = <0x0 0xfdf66200 0x0 0x20>;
1143 reg = <0x0 0xfdf66400 0x0 0x20>;
1148 reg = <0x0 0xfdf66600 0x0 0x20>;
1153 reg = <0x0 0xfdf66800 0x0 0x20>;
1158 reg = <0x0 0xfdf66a00 0x0 0x20>;
1163 reg = <0x0 0xfdf66c00 0x0 0x20>;
1168 reg = <0x0 0xfdf66e00 0x0 0x20>;
1173 reg = <0x0 0xfdf67000 0x0 0x20>;
1178 reg = <0x0 0xfdf67200 0x0 0x20>;
1183 reg = <0x0 0xfdf70000 0x0 0x20>;
1188 reg = <0x0 0xfdf71000 0x0 0x20>;
1193 reg = <0x0 0xfdf72000 0x0 0x20>;
1198 reg = <0x0 0xfdf72200 0x0 0x20>;
1203 reg = <0x0 0xfdf72400 0x0 0x20>;
1208 reg = <0x0 0xfdf80000 0x0 0x20>;
1213 reg = <0x0 0xfdf81000 0x0 0x20>;
1218 reg = <0x0 0xfdf81200 0x0 0x20>;
1223 reg = <0x0 0xfdf82000 0x0 0x20>;
1228 reg = <0x0 0xfdf82200 0x0 0x20>;
1233 bus-range = <0x30 0x3f>;
1241 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1242 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1243 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1244 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1245 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1248 interrupt-map-mask = <0 0 0 7>;
1249 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1250 <0 0 0 2 &pcie2x1l1_intc 1>,
1251 <0 0 0 3 &pcie2x1l1_intc 2>,
1252 <0 0 0 4 &pcie2x1l1_intc 3>;
1255 msi-map = <0x3000 &its0 0x3000 0x1000>;
1260 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1261 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1262 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1263 reg = <0xa 0x40c00000 0x0 0x00400000>,
1264 <0x0 0xfe180000 0x0 0x00010000>,
1265 <0x0 0xf3000000 0x0 0x00100000>;
1275 #address-cells = <0>;
1278 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1284 bus-range = <0x40 0x4f>;
1292 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1293 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1294 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1295 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1296 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1299 interrupt-map-mask = <0 0 0 7>;
1300 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1301 <0 0 0 2 &pcie2x1l2_intc 1>,
1302 <0 0 0 3 &pcie2x1l2_intc 2>,
1303 <0 0 0 4 &pcie2x1l2_intc 3>;
1306 msi-map = <0x4000 &its0 0x4000 0x1000>;
1311 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1312 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1313 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1314 reg = <0xa 0x41000000 0x0 0x00400000>,
1315 <0x0 0xfe190000 0x0 0x00010000>,
1316 <0x0 0xf4000000 0x0 0x00100000>;
1326 #address-cells = <0>;
1329 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1335 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1336 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1337 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1359 #address-cells = <0x1>;
1360 #size-cells = <0x0>;
1364 snps,blen = <0 0 0 0 16 8 4>;
1384 reg = <0 0xfe210000 0 0x1000>;
1385 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1390 ports-implemented = <0x1>;
1392 #size-cells = <0>;
1395 sata-port@0 {
1396 reg = <0>;
1407 reg = <0 0xfe230000 0 0x1000>;
1408 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1413 ports-implemented = <0x1>;
1415 #size-cells = <0>;
1418 sata-port@0 {
1419 reg = <0>;
1430 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1431 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1435 fifo-depth = <0x100>;
1438 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1445 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1446 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1450 fifo-depth = <0x100>;
1453 pinctrl-0 = <&sdiom1_pins>;
1460 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1461 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1469 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1481 reg = <0x0 0xfe470000 0x0 0x1000>;
1482 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1487 dmas = <&dmac0 0>, <&dmac0 1>;
1494 pinctrl-0 = <&i2s0_lrck
1504 #sound-dai-cells = <0>;
1510 reg = <0x0 0xfe480000 0x0 0x1000>;
1511 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1520 pinctrl-0 = <&i2s1m0_lrck
1530 #sound-dai-cells = <0>;
1536 reg = <0x0 0xfe490000 0x0 0x1000>;
1537 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1542 dmas = <&dmac1 0>, <&dmac1 1>;
1546 pinctrl-0 = <&i2s2m1_lrck
1550 #sound-dai-cells = <0>;
1556 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1557 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
1566 pinctrl-0 = <&i2s3_lrck
1570 #sound-dai-cells = <0>;
1576 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1577 <0x0 0xfe680000 0 0x100000>; /* GICR */
1578 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
1580 mbi-alias = <0x0 0xfe610000>;
1590 reg = <0x0 0xfe640000 0x0 0x20000>;
1597 reg = <0x0 0xfe660000 0x0 0x20000>;
1603 ppi_partition0: interrupt-partition-0 {
1615 reg = <0x0 0xfea10000 0x0 0x4000>;
1616 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
1617 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
1626 reg = <0x0 0xfea30000 0x0 0x4000>;
1627 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
1628 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
1637 reg = <0x0 0xfea90000 0x0 0x1000>;
1640 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
1641 pinctrl-0 = <&i2c1m0_xfer>;
1644 #size-cells = <0>;
1650 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1653 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
1654 pinctrl-0 = <&i2c2m0_xfer>;
1657 #size-cells = <0>;
1663 reg = <0x0 0xfeab0000 0x0 0x1000>;
1666 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
1667 pinctrl-0 = <&i2c3m0_xfer>;
1670 #size-cells = <0>;
1676 reg = <0x0 0xfeac0000 0x0 0x1000>;
1679 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
1680 pinctrl-0 = <&i2c4m0_xfer>;
1683 #size-cells = <0>;
1689 reg = <0x0 0xfead0000 0x0 0x1000>;
1692 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
1693 pinctrl-0 = <&i2c5m0_xfer>;
1696 #size-cells = <0>;
1702 reg = <0x0 0xfeae0000 0x0 0x20>;
1703 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
1710 reg = <0x0 0xfeaf0000 0x0 0x100>;
1713 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
1718 reg = <0x0 0xfeb00000 0x0 0x1000>;
1719 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
1725 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1728 #size-cells = <0>;
1734 reg = <0x0 0xfeb10000 0x0 0x1000>;
1735 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
1741 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1744 #size-cells = <0>;
1750 reg = <0x0 0xfeb20000 0x0 0x1000>;
1751 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
1757 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1760 #size-cells = <0>;
1766 reg = <0x0 0xfeb30000 0x0 0x1000>;
1767 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
1773 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1776 #size-cells = <0>;
1782 reg = <0x0 0xfeb40000 0x0 0x100>;
1783 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
1788 pinctrl-0 = <&uart1m1_xfer>;
1797 reg = <0x0 0xfeb50000 0x0 0x100>;
1798 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
1803 pinctrl-0 = <&uart2m1_xfer>;
1812 reg = <0x0 0xfeb60000 0x0 0x100>;
1813 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
1818 pinctrl-0 = <&uart3m1_xfer>;
1827 reg = <0x0 0xfeb70000 0x0 0x100>;
1828 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
1833 pinctrl-0 = <&uart4m1_xfer>;
1842 reg = <0x0 0xfeb80000 0x0 0x100>;
1843 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
1848 pinctrl-0 = <&uart5m1_xfer>;
1857 reg = <0x0 0xfeb90000 0x0 0x100>;
1858 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
1863 pinctrl-0 = <&uart6m1_xfer>;
1872 reg = <0x0 0xfeba0000 0x0 0x100>;
1873 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
1878 pinctrl-0 = <&uart7m1_xfer>;
1887 reg = <0x0 0xfebb0000 0x0 0x100>;
1888 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
1893 pinctrl-0 = <&uart8m1_xfer>;
1902 reg = <0x0 0xfebc0000 0x0 0x100>;
1903 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
1908 pinctrl-0 = <&uart9m1_xfer>;
1917 reg = <0x0 0xfebd0000 0x0 0x10>;
1920 pinctrl-0 = <&pwm4m0_pins>;
1928 reg = <0x0 0xfebd0010 0x0 0x10>;
1931 pinctrl-0 = <&pwm5m0_pins>;
1939 reg = <0x0 0xfebd0020 0x0 0x10>;
1942 pinctrl-0 = <&pwm6m0_pins>;
1950 reg = <0x0 0xfebd0030 0x0 0x10>;
1953 pinctrl-0 = <&pwm7m0_pins>;
1961 reg = <0x0 0xfebe0000 0x0 0x10>;
1964 pinctrl-0 = <&pwm8m0_pins>;
1972 reg = <0x0 0xfebe0010 0x0 0x10>;
1975 pinctrl-0 = <&pwm9m0_pins>;
1983 reg = <0x0 0xfebe0020 0x0 0x10>;
1986 pinctrl-0 = <&pwm10m0_pins>;
1994 reg = <0x0 0xfebe0030 0x0 0x10>;
1997 pinctrl-0 = <&pwm11m0_pins>;
2005 reg = <0x0 0xfebf0000 0x0 0x10>;
2008 pinctrl-0 = <&pwm12m0_pins>;
2016 reg = <0x0 0xfebf0010 0x0 0x10>;
2019 pinctrl-0 = <&pwm13m0_pins>;
2027 reg = <0x0 0xfebf0020 0x0 0x10>;
2030 pinctrl-0 = <&pwm14m0_pins>;
2038 reg = <0x0 0xfebf0030 0x0 0x10>;
2041 pinctrl-0 = <&pwm15m0_pins>;
2049 reg = <0x0 0xfec00000 0x0 0x400>;
2050 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2058 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2059 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2060 pinctrl-0 = <&tsadc_gpio_func>;
2069 reg = <0x0 0xfec10000 0x0 0x10000>;
2070 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2081 reg = <0x0 0xfec80000 0x0 0x1000>;
2084 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2085 pinctrl-0 = <&i2c6m0_xfer>;
2088 #size-cells = <0>;
2094 reg = <0x0 0xfec90000 0x0 0x1000>;
2097 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2098 pinctrl-0 = <&i2c7m0_xfer>;
2101 #size-cells = <0>;
2107 reg = <0x0 0xfeca0000 0x0 0x1000>;
2110 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2111 pinctrl-0 = <&i2c8m0_xfer>;
2114 #size-cells = <0>;
2120 reg = <0x0 0xfecb0000 0x0 0x1000>;
2121 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2127 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2130 #size-cells = <0>;
2136 reg = <0x0 0xfecc0000 0x0 0x400>;
2147 reg = <0x02 0x2>;
2151 reg = <0x07 0x10>;
2155 reg = <0x17 0x1>;
2159 reg = <0x18 0x1>;
2163 reg = <0x19 0x1>;
2167 reg = <0x1a 0x1>;
2171 reg = <0x1b 0x1>;
2175 reg = <0x1c 0x1>;
2180 reg = <0x28 0x1>;
2184 reg = <0x29 0x1>;
2190 reg = <0x0 0xfed10000 0x0 0x4000>;
2191 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2192 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2201 reg = <0x0 0xfee00000 0x0 0x100>;
2217 reg = <0x0 0xfee20000 0x0 0x100>;
2233 reg = <0x0 0xff001000 0x0 0xef000>;
2234 ranges = <0x0 0x0 0xff001000 0xef000>;
2248 reg = <0x0 0xfd8a0000 0x0 0x100>;
2249 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2252 gpio-ranges = <&pinctrl 0 0 32>;
2260 reg = <0x0 0xfec20000 0x0 0x100>;
2261 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2264 gpio-ranges = <&pinctrl 0 32 32>;
2272 reg = <0x0 0xfec30000 0x0 0x100>;
2273 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2276 gpio-ranges = <&pinctrl 0 64 32>;
2284 reg = <0x0 0xfec40000 0x0 0x100>;
2285 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2288 gpio-ranges = <&pinctrl 0 96 32>;
2296 reg = <0x0 0xfec50000 0x0 0x100>;
2297 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2300 gpio-ranges = <&pinctrl 0 128 32>;