Lines Matching +full:0 +full:xfc800000
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
65 reg = <0x0 0x100>;
74 reg = <0x0 0x200>;
83 reg = <0x0 0x300>;
90 cpu0_opp_table: opp-table-0 {
140 arm,smc-id = <0x82000010>;
143 #size-cells = <0>;
146 reg = <0x14>;
229 #clock-cells = <0>;
236 pinctrl-0 = <&clk32k_out0>;
238 #clock-cells = <0>;
243 reg = <0x0 0x0010f000 0x0 0x100>;
246 ranges = <0 0x0 0x0010f000 0x100>;
248 scmi_shmem: sram@0 {
250 reg = <0x0 0x100>;
256 reg = <0 0xfc400000 0 0x1000>;
263 ports-implemented = <0x1>;
270 reg = <0 0xfc800000 0 0x1000>;
277 ports-implemented = <0x1>;
284 reg = <0x0 0xfcc00000 0x0 0x400000>;
300 reg = <0x0 0xfd000000 0x0 0x400000>;
318 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
319 <0x0 0xfd460000 0 0x80000>; /* GICR */
323 mbi-alias = <0x0 0xfd410000>;
330 reg = <0x0 0xfd800000 0x0 0x40000>;
341 reg = <0x0 0xfd840000 0x0 0x40000>;
352 reg = <0x0 0xfd880000 0x0 0x40000>;
363 reg = <0x0 0xfd8c0000 0x0 0x40000>;
374 reg = <0x0 0xfdc20000 0x0 0x10000>;
383 reg = <0x0 0xfdc50000 0x0 0x1000>;
388 reg = <0x0 0xfdc60000 0x0 0x10000>;
393 reg = <0x0 0xfdc80000 0x0 0x1000>;
398 reg = <0x0 0xfdc90000 0x0 0x1000>;
403 reg = <0x0 0xfdca0000 0x0 0x8000>;
408 reg = <0x0 0xfdca8000 0x0 0x8000>;
413 reg = <0x0 0xfdd00000 0x0 0x1000>;
420 reg = <0x0 0xfdd20000 0x0 0x1000>;
433 reg = <0x0 0xfdd40000 0x0 0x1000>;
437 pinctrl-0 = <&i2c0_xfer>;
440 #size-cells = <0>;
446 reg = <0x0 0xfdd50000 0x0 0x100>;
450 dmas = <&dmac0 0>, <&dmac0 1>;
451 pinctrl-0 = <&uart0_xfer>;
460 reg = <0x0 0xfdd70000 0x0 0x10>;
463 pinctrl-0 = <&pwm0m0_pins>;
471 reg = <0x0 0xfdd70010 0x0 0x10>;
474 pinctrl-0 = <&pwm1m0_pins>;
482 reg = <0x0 0xfdd70020 0x0 0x10>;
485 pinctrl-0 = <&pwm2m0_pins>;
493 reg = <0x0 0xfdd70030 0x0 0x10>;
496 pinctrl-0 = <&pwm3_pins>;
504 reg = <0x0 0xfdd90000 0x0 0x1000>;
510 #size-cells = <0>;
518 #power-domain-cells = <0>;
529 #power-domain-cells = <0>;
540 #power-domain-cells = <0>;
553 #power-domain-cells = <0>;
560 #power-domain-cells = <0>;
567 #power-domain-cells = <0>;
576 #power-domain-cells = <0>;
583 reg = <0x0 0xfde60000 0x0 0x4000>;
598 reg = <0x0 0xfdea0000 0x0 0x800>;
609 reg = <0x0 0xfdea0800 0x0 0x40>;
614 #iommu-cells = <0>;
619 reg = <0x0 0xfdeb0000 0x0 0x180>;
630 reg = <0x0 0xfdee0000 0x0 0x800>;
640 reg = <0x0 0xfdee0800 0x0 0x40>;
645 #iommu-cells = <0>;
650 reg = <0x0 0xfe000000 0x0 0x4000>;
655 fifo-depth = <0x100>;
664 reg = <0x0 0xfe010000 0x0 0x10000>;
688 #address-cells = <0x1>;
689 #size-cells = <0x0>;
693 snps,blen = <0 0 0 0 16 8 4>;
710 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
723 #size-cells = <0>;
725 vp0: port@0 {
726 reg = <0>;
728 #size-cells = <0>;
734 #size-cells = <0>;
740 #size-cells = <0>;
747 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
751 #iommu-cells = <0>;
758 reg = <0x00 0xfe060000 0x00 0x10000>;
772 #size-cells = <0>;
774 dsi0_in: port@0 {
775 reg = <0>;
786 reg = <0x0 0xfe070000 0x0 0x10000>;
800 #size-cells = <0>;
802 dsi1_in: port@0 {
803 reg = <0>;
814 reg = <0x0 0xfe0a0000 0x0 0x20000>;
823 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
827 #sound-dai-cells = <0>;
832 #size-cells = <0>;
834 hdmi_in: port@0 {
835 reg = <0>;
846 reg = <0x0 0xfe128000 0x0 0x20>;
851 reg = <0x0 0xfe138080 0x0 0x20>;
856 reg = <0x0 0xfe138100 0x0 0x20>;
861 reg = <0x0 0xfe138180 0x0 0x20>;
866 reg = <0x0 0xfe148000 0x0 0x20>;
871 reg = <0x0 0xfe148080 0x0 0x20>;
876 reg = <0x0 0xfe148100 0x0 0x20>;
881 reg = <0x0 0xfe150000 0x0 0x20>;
886 reg = <0x0 0xfe158000 0x0 0x20>;
891 reg = <0x0 0xfe158100 0x0 0x20>;
896 reg = <0x0 0xfe158180 0x0 0x20>;
901 reg = <0x0 0xfe158200 0x0 0x20>;
906 reg = <0x0 0xfe158280 0x0 0x20>;
911 reg = <0x0 0xfe158300 0x0 0x20>;
916 reg = <0x0 0xfe180000 0x0 0x20>;
921 reg = <0x0 0xfe190000 0x0 0x20>;
926 reg = <0x0 0xfe190280 0x0 0x20>;
931 reg = <0x0 0xfe190300 0x0 0x20>;
936 reg = <0x0 0xfe190380 0x0 0x20>;
941 reg = <0x0 0xfe190400 0x0 0x20>;
946 reg = <0x0 0xfe198000 0x0 0x20>;
951 reg = <0x0 0xfe1a8000 0x0 0x20>;
956 reg = <0x0 0xfe1a8080 0x0 0x20>;
961 reg = <0x0 0xfe1a8100 0x0 0x20>;
966 reg = <0x3 0xc0000000 0x0 0x00400000>,
967 <0x0 0xfe260000 0x0 0x00010000>,
968 <0x0 0xf4000000 0x0 0x00100000>;
976 bus-range = <0x0 0xf>;
984 interrupt-map-mask = <0 0 0 7>;
985 interrupt-map = <0 0 0 1 &pcie_intc 0>,
986 <0 0 0 2 &pcie_intc 1>,
987 <0 0 0 3 &pcie_intc 2>,
988 <0 0 0 4 &pcie_intc 3>;
989 linux,pci-domain = <0>;
993 msi-map = <0x0 &gic 0x0 0x1000>;
998 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
999 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
1000 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
1008 #address-cells = <0>;
1018 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1023 fifo-depth = <0x100>;
1032 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1037 fifo-depth = <0x100>;
1046 reg = <0x0 0xfe300000 0x0 0x4000>;
1050 pinctrl-0 = <&fspi_pins>;
1057 reg = <0x0 0xfe310000 0x0 0x10000>;
1070 reg = <0x0 0xfe400000 0x0 0x1000>;
1076 dmas = <&dmac1 0>;
1081 #sound-dai-cells = <0>;
1087 reg = <0x0 0xfe410000 0x0 0x1000>;
1100 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1106 #sound-dai-cells = <0>;
1112 reg = <0x0 0xfe420000 0x0 0x1000>;
1124 pinctrl-0 = <&i2s2m0_sclktx
1128 #sound-dai-cells = <0>;
1134 reg = <0x0 0xfe430000 0x0 0x1000>;
1144 #sound-dai-cells = <0>;
1150 reg = <0x0 0xfe440000 0x0 0x1000>;
1156 pinctrl-0 = <&pdmm0_clk
1165 #sound-dai-cells = <0>;
1171 reg = <0x0 0xfe460000 0x0 0x1000>;
1178 pinctrl-0 = <&spdifm0_tx>;
1179 #sound-dai-cells = <0>;
1185 reg = <0x0 0xfe530000 0x0 0x4000>;
1196 reg = <0x0 0xfe550000 0x0 0x4000>;
1207 reg = <0x0 0xfe5a0000 0x0 0x1000>;
1211 pinctrl-0 = <&i2c1_xfer>;
1214 #size-cells = <0>;
1220 reg = <0x0 0xfe5b0000 0x0 0x1000>;
1224 pinctrl-0 = <&i2c2m0_xfer>;
1227 #size-cells = <0>;
1233 reg = <0x0 0xfe5c0000 0x0 0x1000>;
1237 pinctrl-0 = <&i2c3m0_xfer>;
1240 #size-cells = <0>;
1246 reg = <0x0 0xfe5d0000 0x0 0x1000>;
1250 pinctrl-0 = <&i2c4m0_xfer>;
1253 #size-cells = <0>;
1259 reg = <0x0 0xfe5e0000 0x0 0x1000>;
1263 pinctrl-0 = <&i2c5m0_xfer>;
1266 #size-cells = <0>;
1272 reg = <0x0 0xfe600000 0x0 0x100>;
1280 reg = <0x0 0xfe610000 0x0 0x1000>;
1287 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1289 #size-cells = <0>;
1295 reg = <0x0 0xfe620000 0x0 0x1000>;
1302 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1304 #size-cells = <0>;
1310 reg = <0x0 0xfe630000 0x0 0x1000>;
1317 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1319 #size-cells = <0>;
1325 reg = <0x0 0xfe640000 0x0 0x1000>;
1332 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1334 #size-cells = <0>;
1340 reg = <0x0 0xfe650000 0x0 0x100>;
1345 pinctrl-0 = <&uart1m0_xfer>;
1354 reg = <0x0 0xfe660000 0x0 0x100>;
1359 pinctrl-0 = <&uart2m0_xfer>;
1368 reg = <0x0 0xfe670000 0x0 0x100>;
1373 pinctrl-0 = <&uart3m0_xfer>;
1382 reg = <0x0 0xfe680000 0x0 0x100>;
1387 pinctrl-0 = <&uart4m0_xfer>;
1396 reg = <0x0 0xfe690000 0x0 0x100>;
1401 pinctrl-0 = <&uart5m0_xfer>;
1410 reg = <0x0 0xfe6a0000 0x0 0x100>;
1415 pinctrl-0 = <&uart6m0_xfer>;
1424 reg = <0x0 0xfe6b0000 0x0 0x100>;
1429 pinctrl-0 = <&uart7m0_xfer>;
1438 reg = <0x0 0xfe6c0000 0x0 0x100>;
1443 pinctrl-0 = <&uart8m0_xfer>;
1452 reg = <0x0 0xfe6d0000 0x0 0x100>;
1457 pinctrl-0 = <&uart9m0_xfer>;
1469 thermal-sensors = <&tsadc 0>;
1537 reg = <0x0 0xfe710000 0x0 0x100>;
1548 pinctrl-0 = <&tsadc_pin>;
1557 reg = <0x0 0xfe720000 0x0 0x100>;
1569 reg = <0x0 0xfe6e0000 0x0 0x10>;
1572 pinctrl-0 = <&pwm4_pins>;
1580 reg = <0x0 0xfe6e0010 0x0 0x10>;
1583 pinctrl-0 = <&pwm5_pins>;
1591 reg = <0x0 0xfe6e0020 0x0 0x10>;
1594 pinctrl-0 = <&pwm6_pins>;
1602 reg = <0x0 0xfe6e0030 0x0 0x10>;
1605 pinctrl-0 = <&pwm7_pins>;
1613 reg = <0x0 0xfe6f0000 0x0 0x10>;
1616 pinctrl-0 = <&pwm8m0_pins>;
1624 reg = <0x0 0xfe6f0010 0x0 0x10>;
1627 pinctrl-0 = <&pwm9m0_pins>;
1635 reg = <0x0 0xfe6f0020 0x0 0x10>;
1638 pinctrl-0 = <&pwm10m0_pins>;
1646 reg = <0x0 0xfe6f0030 0x0 0x10>;
1649 pinctrl-0 = <&pwm11m0_pins>;
1657 reg = <0x0 0xfe700000 0x0 0x10>;
1660 pinctrl-0 = <&pwm12m0_pins>;
1668 reg = <0x0 0xfe700010 0x0 0x10>;
1671 pinctrl-0 = <&pwm13m0_pins>;
1679 reg = <0x0 0xfe700020 0x0 0x10>;
1682 pinctrl-0 = <&pwm14m0_pins>;
1690 reg = <0x0 0xfe700030 0x0 0x10>;
1693 pinctrl-0 = <&pwm15m0_pins>;
1701 reg = <0x0 0xfe830000 0x0 0x100>;
1717 reg = <0x0 0xfe840000 0x0 0x100>;
1733 reg = <0x0 0xfe870000 0x0 0x10000>;
1736 #phy-cells = <0>;
1745 reg = <0x0 0xfe850000 0x0 0x10000>;
1748 #phy-cells = <0>;
1757 reg = <0x0 0xfe860000 0x0 0x10000>;
1760 #phy-cells = <0>;
1769 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1775 #clock-cells = <0>;
1779 #phy-cells = <0>;
1784 #phy-cells = <0>;
1791 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1797 #clock-cells = <0>;
1801 #phy-cells = <0>;
1806 #phy-cells = <0>;
1821 reg = <0x0 0xfdd60000 0x0 0x100>;
1825 gpio-ranges = <&pinctrl 0 0 32>;
1833 reg = <0x0 0xfe740000 0x0 0x100>;
1837 gpio-ranges = <&pinctrl 0 32 32>;
1845 reg = <0x0 0xfe750000 0x0 0x100>;
1849 gpio-ranges = <&pinctrl 0 64 32>;
1857 reg = <0x0 0xfe760000 0x0 0x100>;
1861 gpio-ranges = <&pinctrl 0 96 32>;
1869 reg = <0x0 0xfe770000 0x0 0x100>;
1873 gpio-ranges = <&pinctrl 0 128 32>;