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/openbmc/linux/arch/arm/mach-spear/
H A Dspear1310.c21 #define SPEAR1310_RAS_GRP1_BASE UL(0xD8000000)
22 #define VA_SPEAR1310_RAS_GRP1_BASE UL(0xFA000000)
26 platform_device_register_simple("spear-cpufreq", -1, NULL, 0); in spear1310_dt_init()
38 * 0xD8000000 0xFA000000
/openbmc/linux/arch/arm/mach-omap2/
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/openbmc/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Drockchip,rk3399-pcie.yaml61 const: 0
98 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
99 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
100 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
103 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
104 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
106 msi-map = <0x0 &its 0x0 0x1000>;
107 reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
118 pinctrl-0 = <&pcie_clkreq>;
120 interrupt-map-mask = <0 0 0 7>;
[all …]
H A Drockchip,rk3399-pcie-ep.yaml50 reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
63 phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
64 phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
67 pinctrl-0 = <&pcie_clkreqnb_cpm>;
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_s10.h9 #define SOCFPGA_CCU_ADDRESS 0xf7000000
10 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
11 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
12 #define SOCFPGA_SDR_ADDRESS 0xf8011000
13 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
14 #define SOCFPGA_SMMU_ADDRESS 0xfa000000
15 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
16 #define SOCFPGA_UART0_ADDRESS 0xffc02000
17 #define SOCFPGA_UART1_ADDRESS 0xffc02100
18 #define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
[all …]
/openbmc/u-boot/doc/mvebu/
H A Darmada-8k-memory.txt13 0x00000000 0xEFFFFFFF DRAM
15 0xF0000000 0xF0FFFFFF AP Internal registers space
17 0xF1000000 0xF1FFFFFF Reserved.
19 0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers
22 0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers
25 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space.
27 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space.
29 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space.
31 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space.
33 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space.
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dhardware.h42 #define PCMCIA_IO_0_BASE 0xf6000000
43 #define PCMCIA_IO_1_BASE 0xf7000000
49 #define PCIO_BASE 0
55 #define UNCACHED_PHYS_0 0xff000000
61 * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
62 * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
63 * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-80x0.dtsi24 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
45 #define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
/openbmc/u-boot/arch/arm/dts/
H A Darmada-cp110-slave.dtsi62 ranges = <0x0 0x0 0xf4000000 0x2000000>;
64 cps_ethernet: ethernet@0 {
66 reg = <0x0 0x100000>, <0x129000 0xb000>;
74 port-id = <0>;
75 gop-port-id = <0>;
96 #size-cells = <0>;
98 reg = <0x12a200 0x10>;
104 reg = <0x440000 0x1000>;
125 reg = <0x440000 0x20>;
127 max-func = <0xf>;
[all …]
/openbmc/u-boot/include/configs/
H A DMPC8313ERDB.h30 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
32 #define CONFIG_SPL_PAD_TO 0x4000
35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
38 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
39 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
73 #define CONFIG_SYS_IMMR 0xE0000000
79 #define CONFIG_SYS_MEMTEST_START 0x00001000
80 #define CONFIG_SYS_MEMTEST_END 0x07f00000
88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
[all …]
/openbmc/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h22 ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
37 ORION5X_TARGET_DRAM = 0,
45 ORION5X_ATTR_DRAM_CS0 = 0x0e,
46 ORION5X_ATTR_DRAM_CS1 = 0x0d,
47 ORION5X_ATTR_DRAM_CS2 = 0x0b,
48 ORION5X_ATTR_DRAM_CS3 = 0x07,
49 ORION5X_ATTR_PCI_MEM = 0x59,
50 ORION5X_ATTR_PCI_IO = 0x51,
51 ORION5X_ATTR_PCIE_MEM = 0x59,
52 ORION5X_ATTR_PCIE_IO = 0x51,
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dep8248e.dts26 #size-cells = <0>;
28 PowerPC,8248@0 {
30 reg = <0>;
35 timebase-frequency = <0>;
36 clock-frequency = <0>;
46 reg = <0xf0010100 0x40>;
48 ranges = <0 0 0xfc000000 0x04000000
49 1 0 0xfa000000 0x00008000>;
51 flash@0,3800000 {
53 reg = <0 0x3800000 0x800000>;
[all …]
H A Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
H A Dmpc8308rdb.dts26 #size-cells = <0>;
28 PowerPC,8308@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8313erdb.dts26 #size-cells = <0>;
28 PowerPC,8313@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8379_rdb.dts25 #size-cells = <0>;
27 PowerPC,8379@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
56 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8315erdb.dts27 #size-cells = <0>;
29 PowerPC,8315@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x08000000>; // 128MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8377_rdb.dts27 #size-cells = <0>;
29 PowerPC,8377@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8378_rdb.dts27 #size-cells = <0>;
29 PowerPC,8378@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dkmcent2.dts27 size = <0 0x1000000>;
28 alignment = <0 0x1000000>;
31 size = <0 0x400000>;
32 alignment = <0 0x400000>;
35 size = <0 0x2000000>;
36 alignment = <0 0x2000000>;
41 reg = <0xf 0xfe124000 0 0x2000>;
42 ranges = <0 0 0xf 0xe8000000 0x04000000
43 1 0 0xf 0xfa000000 0x00010000
44 2 0 0xf 0xfb000000 0x00010000
[all …]
/openbmc/linux/arch/arm/mach-sa1100/
H A Dgeneric.c70 return 0; in sa11x0_getspeed()
71 return sa11x0_freq_table[PPCR & 0xf].frequency; in sa11x0_getspeed()
89 PSPR = 0; in sa1100_power_off()
99 /* Jump into ROM at address 0 */ in sa11x0_restart()
100 soft_restart(0); in sa11x0_restart()
119 [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
123 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
130 .coherent_dma_mask = 0xffffffff,
137 [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
149 [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dphy.c52 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92ee_phy_query_bb_reg()
142 u8 rfpi_enable = 0; in _rtl92ee_phy_rf_serial_read()
145 offset &= 0xff; in _rtl92ee_phy_rf_serial_read()
149 return 0xFFFFFFFF; in _rtl92ee_phy_rf_serial_read()
175 "RFR-%d Addr[0x%x]=0x%x\n", in _rtl92ee_phy_rf_serial_read()
194 offset &= 0xff; in _rtl92ee_phy_rf_serial_write()
196 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92ee_phy_rf_serial_write()
199 "RFW-%d Addr[0x%x]=0x%x\n", rfpath, in _rtl92ee_phy_rf_serial_write()
219 regval | BIT(13) | BIT(0) | BIT(1)); in rtl92ee_phy_bb_config()
226 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92ee_phy_bb_config()
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi46 #size-cells = <0>;
48 cpu@0 {
51 reg = <0>;
55 xxti: oscillator-0 {
57 clock-frequency = <0>;
59 #clock-cells = <0>;
64 clock-frequency = <0>;
66 #clock-cells = <0>;
77 reg = <0xb0600000 0x2000>,
78 <0xb0000000 0x20000>,
[all …]

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