xref: /openbmc/u-boot/doc/mvebu/armada-8k-memory.txt (revision 0d92f2141ac5ef5c80d13e9501890f914525d43c)
1*0d92f214SKonstantin Porotchkin		     Memory Layout on Armada-8k SoC's
2*0d92f214SKonstantin Porotchkin		     ================================
3*0d92f214SKonstantin Porotchkin
4*0d92f214SKonstantin PorotchkinThe below desribes the physical memory layout for Marvell's Armada-8k SoC's.
5*0d92f214SKonstantin Porotchkin
6*0d92f214SKonstantin PorotchkinThis assumes that the SoC includes Dual CP configuration, in case the flavor is using
7*0d92f214SKonstantin Porotchkina single CP configuration, then all secondary-CP mappings are invalid.
8*0d92f214SKonstantin Porotchkin
9*0d92f214SKonstantin PorotchkinAll "Reserved" areas below, are kept for future usage.
10*0d92f214SKonstantin Porotchkin
11*0d92f214SKonstantin PorotchkinStart		End			Use
12*0d92f214SKonstantin Porotchkin--------------------------------------------------------------------------
13*0d92f214SKonstantin Porotchkin0x00000000	0xEFFFFFFF		DRAM
14*0d92f214SKonstantin Porotchkin
15*0d92f214SKonstantin Porotchkin0xF0000000	0xF0FFFFFF		AP Internal registers space
16*0d92f214SKonstantin Porotchkin
17*0d92f214SKonstantin Porotchkin0xF1000000	0xF1FFFFFF		Reserved.
18*0d92f214SKonstantin Porotchkin
19*0d92f214SKonstantin Porotchkin0xF2000000	0xF3FFFFFF		CP-0 Internal (configuration) registers
20*0d92f214SKonstantin Porotchkin					space.
21*0d92f214SKonstantin Porotchkin
22*0d92f214SKonstantin Porotchkin0xF4000000	0xF5FFFFFF		CP-1 Internal (configuration) registers
23*0d92f214SKonstantin Porotchkin					space.
24*0d92f214SKonstantin Porotchkin
25*0d92f214SKonstantin Porotchkin0xF6000000	0xF6FFFFFF		CP-0 / PCIe#0 Memory space.
26*0d92f214SKonstantin Porotchkin
27*0d92f214SKonstantin Porotchkin0xF7000000	0xF7FFFFFF		CP-0 / PCIe#1 Memory space.
28*0d92f214SKonstantin Porotchkin
29*0d92f214SKonstantin Porotchkin0xF8000000	0xF8FFFFFF		CP-0 / PCIe#2 Memory space.
30*0d92f214SKonstantin Porotchkin
31*0d92f214SKonstantin Porotchkin0xF9000000	0xF900FFFF		CP-0 / PCIe#0 IO space.
32*0d92f214SKonstantin Porotchkin
33*0d92f214SKonstantin Porotchkin0xF9010000	0xF901FFFF		CP-0 / PCIe#1 IO space.
34*0d92f214SKonstantin Porotchkin
35*0d92f214SKonstantin Porotchkin0xF9020000	0xF902FFFF		CP-0 / PCIe#2 IO space.
36*0d92f214SKonstantin Porotchkin
37*0d92f214SKonstantin Porotchkin0xF9030000	0xF9FFFFFF		Reserved.
38*0d92f214SKonstantin Porotchkin
39*0d92f214SKonstantin Porotchkin0xFA000000	0xFAFFFFFF		CP-1 / PCIe#0 Memory space.
40*0d92f214SKonstantin Porotchkin
41*0d92f214SKonstantin Porotchkin0xFB000000	0xFBFFFFFF		CP-1 / PCIe#1 Memory space.
42*0d92f214SKonstantin Porotchkin
43*0d92f214SKonstantin Porotchkin0xFC000000	0xFCFFFFFF		CP-1 / PCIe#2 Memory space.
44*0d92f214SKonstantin Porotchkin
45*0d92f214SKonstantin Porotchkin0xFD000000	0xFD00FFFF		CP-1 / PCIe#0 IO space.
46*0d92f214SKonstantin Porotchkin
47*0d92f214SKonstantin Porotchkin0xFD010000	0xFD01FFFF		CP-1 / PCIe#1 IO space.
48*0d92f214SKonstantin Porotchkin
49*0d92f214SKonstantin Porotchkin0xFD020000	0xFD02FFFF		CP-1 / PCIe#2 IO space.
50*0d92f214SKonstantin Porotchkin
51*0d92f214SKonstantin Porotchkin0xFD030000	0xFFEFFFFF		Reserved.
52*0d92f214SKonstantin Porotchkin
53*0d92f214SKonstantin Porotchkin0xFFF00000	0xFFFFFFFF		Bootrom
54*0d92f214SKonstantin Porotchkin
55*0d92f214SKonstantin Porotchkin0x100000000	<DRAM Size>-1		DRAM
56*0d92f214SKonstantin Porotchkin
57