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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Darm,pl353-nand-r2p1.yaml37 reg = <0xe000e000 0x0001000>;
40 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
46 nfc0: nand-controller@0,0 {
48 reg = <0 0 0x1000000>;
50 #size-cells = <0>;
/openbmc/u-boot/arch/arm/include/asm/
H A Darmv7m.h14 #define V7M_SCS_BASE 0xE000E000
15 #define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100)
16 #define V7M_SCB_BASE (V7M_SCS_BASE + 0x0D00)
17 #define V7M_PROC_FTR_BASE (V7M_SCS_BASE + 0x0D78)
18 #define V7M_MPU_BASE (V7M_SCS_BASE + 0x0D90)
19 #define V7M_FPU_BASE (V7M_SCS_BASE + 0x0F30)
20 #define V7M_CACHE_MAINT_BASE (V7M_SCS_BASE + 0x0F50)
21 #define V7M_ACCESS_CNTL_BASE (V7M_SCS_BASE + 0x0F90)
23 #define V7M_SCB_VTOR 0x08
31 uint32_t scr; /* offset 0x10: System Control Register */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl35x-smc.yaml33 pattern: "^memory-controller@[0-9a-f]+$"
69 - description: Combined or Memory interface 0 IRQ
73 "@[0-7],[a-f0-9]+$":
91 minimum: 0
141 reg = <0xe000e000 0x0001000>;
144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
150 nfc0: nand-controller@0,0 {
152 reg = <0 0 0x1000000>;
[all …]
/openbmc/u-boot/arch/arm/mach-zynq/include/mach/
H A Dhardware.h9 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
10 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
11 #define ZYNQ_SCU_BASEADDR 0xF8F00000
12 #define ZYNQ_QSPI_BASEADDR 0xE000D000
13 #define ZYNQ_SMC_BASEADDR 0xE000E000
14 #define ZYNQ_NAND_BASEADDR 0xE1000000
15 #define ZYNQ_DDRC_BASEADDR 0xF8006000
16 #define ZYNQ_EFUSE_BASEADDR 0xF800D000
17 #define ZYNQ_USB_BASEADDR0 0xE0002000
18 #define ZYNQ_USB_BASEADDR1 0xE0003000
[all …]
/openbmc/linux/drivers/mcb/
H A Dmcb-lpc.c26 int ret = 0, table_size; in mcb_lpc_probe()
32 priv->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mcb_lpc_probe()
60 if (ret < 0) { in mcb_lpc_probe()
93 return 0; in mcb_lpc_probe()
106 return 0; in mcb_lpc_remove()
128 return 0; in mcb_lpc_create_platform_device()
135 static struct resource sc24_fpga_resource = DEFINE_RES_MEM(0xe000e000, CHAM_HEADER_SIZE);
136 static struct resource sc31_fpga_resource = DEFINE_RES_MEM(0xf000e000, CHAM_HEADER_SIZE);
/openbmc/qemu/hw/arm/
H A Darmv7m.c34 return s->base | (offset & 0x1ffffff) >> 5; in bitband_addr()
107 "bitband", 0x02000000); in bitband_init()
126 0x20000000, 0x40000000
130 0x22000000, 0x42000000
141 attrs.secure = 0; in v7m_sysreg_ns_write()
161 attrs.secure = 0; in v7m_sysreg_ns_read()
169 *data = 0; in v7m_sysreg_ns_read()
188 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); in v7m_systick_write()
201 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); in v7m_systick_read()
220 qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n", in ppb_default_read()
[all …]
H A Dxilinx_zynq.c59 #define MPCORE_PERIPHBASE 0xF8F00000
60 #define ZYNQ_BOARD_MIDR 0x413FC090
66 #define BOARD_SETUP_ADDR 0x100
68 #define SLCR_LOCK_OFFSET 0x004
69 #define SLCR_UNLOCK_OFFSET 0x008
70 #define SLCR_ARM_PLL_OFFSET 0x100
72 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
73 #define SLCR_XILINX_LOCK_KEY 0x767b
75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
77 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
[all …]
/openbmc/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c37 * and one for the unused exception number 0).
44 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
47 * so line 0 is exception 16.
61 #define NVIC_NOEXC_PRIO 0x100
63 #define NVIC_NS_PRIO_LIMIT 0x80
66 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
93 * 0 if there is more than one active exception
107 int irq, nhand = 0; in nvic_rettobase()
116 return 0; in nvic_rettobase()
126 * 0 if no external interrupt is pending
[all …]
/openbmc/qemu/target/arm/
H A Dptw.c94 [0] = 32,
105 for (int i = ARRAY_SIZE(pamax_map) - 1; i >= 0; i--) { in round_down_to_parange_index()
171 * If this is the Secure EL1&0 regime we need to check the NSW and SW bits.
184 * an NS stage 1+2 lookup while the NS bit is 0.) in ptw_idx_for_stage_2()
209 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; in regime_translation_big_endian()
221 if (ttbrn == 0) { in regime_ttbr()
244 case 0: in regime_translation_disabled()
260 return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; in regime_translation_disabled()
275 /* HCR.DC means SCTLR_EL1.M behaves as 0 */ in regime_translation_disabled()
302 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; in regime_translation_disabled()
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852b_table.c10 {0x704, 0x601E0100},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x4018, 0x4F4C084B},
18 {0x401C, 0x084A4E52},
19 {0x4020, 0x4D504E4B},
[all …]
H A Drtw8851b_table.c10 {0x704, 0x601E0500},
11 {0x4000, 0x00000000},
12 {0x4004, 0xCA014000},
13 {0x4008, 0xC751D4F0},
14 {0x400C, 0x44511475},
15 {0x4010, 0x00000000},
16 {0x4014, 0x00000000},
17 {0x47BC, 0x00000380},
18 {0x4018, 0x4F4C084B},
19 {0x401C, 0x084A4E52},
[all …]
H A Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x00000004},
15 {0xF03600FF, 0x00000005},
16 {0x704, 0x601E0100},
17 {0x714, 0x00000000},
18 {0x718, 0x13332333},
19 {0x714, 0x00010000},
[all …]
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x00000004},
15 {0x70C, 0x00000020},
16 {0x704, 0x601E0100},
17 {0x4000, 0x00000000},
18 {0x4004, 0xCA014000},
19 {0x4008, 0xC751D4F0},
[all …]