Lines Matching +full:0 +full:xe000e000
14 #define V7M_SCS_BASE 0xE000E000
15 #define V7M_NVIC_BASE (V7M_SCS_BASE + 0x0100)
16 #define V7M_SCB_BASE (V7M_SCS_BASE + 0x0D00)
17 #define V7M_PROC_FTR_BASE (V7M_SCS_BASE + 0x0D78)
18 #define V7M_MPU_BASE (V7M_SCS_BASE + 0x0D90)
19 #define V7M_FPU_BASE (V7M_SCS_BASE + 0x0F30)
20 #define V7M_CACHE_MAINT_BASE (V7M_SCS_BASE + 0x0F50)
21 #define V7M_ACCESS_CNTL_BASE (V7M_SCS_BASE + 0x0F90)
23 #define V7M_SCB_VTOR 0x08
31 uint32_t scr; /* offset 0x10: System Control Register */
32 uint32_t ccr; /* offset 0x14: Config and Control Register */
33 uint32_t shpr1; /* offset 0x18: System Handler Priority Reg 1 */
34 uint32_t shpr2; /* offset 0x1c: System Handler Priority Reg 2 */
35 uint32_t shpr3; /* offset 0x20: System Handler Priority Reg 3 */
36 uint32_t shcrs; /* offset 0x24: System Handler Control State */
37 uint32_t cfsr; /* offset 0x28: Configurable Fault Status Reg */
38 uint32_t hfsr; /* offset 0x2C: HardFault Status Register */
39 uint32_t res; /* offset 0x30: reserved */
40 uint32_t mmar; /* offset 0x34: MemManage Fault Address Reg */
41 uint32_t bfar; /* offset 0x38: BusFault Address Reg */
42 uint32_t afsr; /* offset 0x3C: Auxiliary Fault Status Reg */
46 #define V7M_AIRCR_VECTKEY 0x5fa
50 #define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT)
53 #define V7M_ICSR_VECTACT_MSK 0xFF