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/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d3_smc.h13 #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600)
14 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604)
15 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608)
16 #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c)
17 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610)
20 u32 setup; /* 0x600 SMC Setup Register */
21 u32 pulse; /* 0x604 SMC Pulse Register */
22 u32 cycle; /* 0x608 SMC Cycle Register */
23 u32 timings; /* 0x60C SMC Cycle Register */
24 u32 mode; /* 0x610 SMC Mode Register */
[all …]
H A Dsama5d2_smc.h13 #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700)
14 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704)
15 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708)
16 #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c)
17 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710)
20 u32 setup; /* 0x600 SMC Setup Register */
21 u32 pulse; /* 0x604 SMC Pulse Register */
22 u32 cycle; /* 0x608 SMC Cycle Register */
23 u32 timings; /* 0x60C SMC Cycle Register */
24 u32 mode; /* 0x610 SMC Mode Register */
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dhandoff_s10.h13 #define S10_HANDOFF_BASE 0xFFE3F000
14 #define S10_HANDOFF_MUX (S10_HANDOFF_BASE + 0x10)
15 #define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0)
16 #define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330)
17 #define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0)
18 #define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580)
19 #define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610)
20 #define S10_HANDOFF_MAGIC_MUX 0x504D5558
21 #define S10_HANDOFF_MAGIC_IOCTL 0x494F4354
22 #define S10_HANDOFF_MAGIC_FPGA 0x46504741
[all …]
/openbmc/u-boot/drivers/sound/
H A Dwm8994_registers.h12 #define WM8994_SOFTWARE_RESET 0x00
13 #define WM8994_POWER_MANAGEMENT_1 0x01
14 #define WM8994_POWER_MANAGEMENT_2 0x02
15 #define WM8994_POWER_MANAGEMENT_4 0x04
16 #define WM8994_POWER_MANAGEMENT_5 0x05
17 #define WM8994_LEFT_OUTPUT_VOLUME 0x1C
18 #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
19 #define WM8994_OUTPUT_MIXER_1 0x2D
20 #define WM8994_OUTPUT_MIXER_2 0x2E
21 #define WM8994_CHARGE_PUMP_1 0x4C
[all …]
/openbmc/linux/include/linux/soc/mmp/
H A Dcputype.h12 * PXA168 S0 0x56158400 0x0000C910
13 * PXA168 A0 0x56158400 0x00A0A168
14 * PXA910 Y1 0x56158400 0x00F2C920
15 * PXA910 A0 0x56158400 0x00F2C910
16 * PXA910 A1 0x56158400 0x00A0C910
17 * PXA920 Y0 0x56158400 0x00F2C920
18 * PXA920 A0 0x56158400 0x00A0C920
19 * PXA920 A1 0x56158400 0x00A1C920
20 * MMP2 Z0 0x560f5811 0x00F00410
21 * MMP2 Z1 0x560f5811 0x00E00410
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/openbmc/linux/arch/arm/include/asm/hardware/
H A Dcache-aurora-l2.h14 #define AURORA_SYNC_REG 0x700
15 #define AURORA_RANGE_BASE_ADDR_REG 0x720
16 #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
17 #define AURORA_INVAL_RANGE_REG 0x774
18 #define AURORA_CLEAN_RANGE_REG 0x7b4
19 #define AURORA_FLUSH_RANGE_REG 0x7f4
23 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
25 (0 << AURORA_ACR_REPLACEMENT_OFFSET)
34 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
36 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,emev2-smu.yaml28 const: 0
61 const: 0
92 const: 0
112 reg = <0xe0110000 0x10000>;
114 #size-cells = <0>;
119 #clock-cells = <0>;
126 #clock-cells = <0>;
128 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
130 reg = <0x610 0>;
132 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6q-pinfunc.h17 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
19 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
20 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
21 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
22 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
24 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
25 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
26 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx6dl-pinfunc.h17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dcrossbar.h16 u32 prs1; /* 0x100 Priority Register Slave 1 */
17 u32 res1[3]; /* 0x104 - 0F */
18 u32 crs1; /* 0x110 Control Register Slave 1 */
19 u32 res2[187]; /* 0x114 - 0x3FF */
21 u32 prs4; /* 0x400 Priority Register Slave 4 */
22 u32 res3[3]; /* 0x404 - 0F */
23 u32 crs4; /* 0x410 Control Register Slave 4 */
24 u32 res4[123]; /* 0x414 - 0x5FF */
26 u32 prs6; /* 0x600 Priority Register Slave 6 */
27 u32 res5[3]; /* 0x604 - 0F */
[all …]
/openbmc/u-boot/drivers/phy/
H A Dphy-rcar-gen3.c21 /* USB2.0 Host registers (original offset is +0x200) */
22 #define USB2_INT_ENABLE 0x000
23 #define USB2_USBCTR 0x00c
24 #define USB2_SPD_RSM_TIMSET 0x10c
25 #define USB2_OC_TIMSET 0x110
26 #define USB2_COMMCTRL 0x600
27 #define USB2_OBINTSTA 0x604
28 #define USB2_OBINTEN 0x608
29 #define USB2_VBCTRL 0x60c
30 #define USB2_LINECTRL1 0x610
[all …]
/openbmc/u-boot/board/aspeed/ast2600_intel/
H A Dintel.c9 #define SCU_BASE 0x1e6e2000
10 #define SCU_PINMUX4 (SCU_BASE + 0x410)
12 #define SCU_PINMUX5 (SCU_BASE + 0x414)
17 #define SCU_GPIO_PD0 (SCU_BASE + 0x610)
19 #define SCU_PINMUX27 (SCU_BASE + 0x69c)
23 #define ESPI_BASE 0x1e6ee000
24 #define ESPI_CTRL (ESPI_BASE + 0x0)
25 #define ESPI_INT_EN (ESPI_BASE + 0xc)
26 #define ESPI_CTRL2 (ESPI_BASE + 0x80)
27 #define ESPI_SYSEVT_INT_EN (ESPI_BASE + 0x94)
[all …]
/openbmc/linux/include/linux/mfd/mt6358/
H A Dregisters.h10 #define MT6358_SWCID 0xa
11 #define MT6358_TOPSTATUS 0x28
12 #define MT6358_TOP_RST_MISC 0x14c
13 #define MT6358_MISC_TOP_INT_CON0 0x188
14 #define MT6358_MISC_TOP_INT_STATUS0 0x194
15 #define MT6358_TOP_INT_STATUS0 0x19e
16 #define MT6358_SCK_TOP_INT_CON0 0x52e
17 #define MT6358_SCK_TOP_INT_STATUS0 0x53a
18 #define MT6358_EOSC_CALI_CON0 0x540
19 #define MT6358_EOSC_CALI_CON1 0x542
[all …]
/openbmc/linux/drivers/nvmem/
H A Dvf610-ocotp.c23 #define OCOTP_CTRL_REG 0x00
24 #define OCOTP_CTRL_SET 0x04
25 #define OCOTP_CTRL_CLR 0x08
26 #define OCOTP_TIMING 0x10
27 #define OCOTP_DATA 0x20
28 #define OCOTP_READ_CTRL_REG 0x30
29 #define OCOTP_READ_FUSE_DATA 0x40
33 #define OCOTP_CTRL_WR_UNLOCK_KEY 0x3E77
35 #define OCOTP_CTRL_ADDR 0
36 #define OCOTP_CTRL_ADDR_MASK GENMASK(6, 0)
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dep93xx_adc.c40 #define EP93XX_ADC_RESULT 0x08
42 #define EP93XX_ADC_SWITCH 0x18
43 #define EP93XX_ADC_SW_LOCK 0x20
64 * Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets.
69 EP93XX_ADC_CH(0, "YM", 0x608),
70 EP93XX_ADC_CH(1, "SXP", 0x680),
71 EP93XX_ADC_CH(2, "SXM", 0x640),
72 EP93XX_ADC_CH(3, "SYP", 0x620),
73 EP93XX_ADC_CH(4, "SYM", 0x610),
74 EP93XX_ADC_CH(5, "XP", 0x601),
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx5/
H A Diomux-mx51.h47 MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
48 MX51_PAD_EIM_D17__GPIO2_1 = IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
49 MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
50 MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
51 MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
52 MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
53 MX51_PAD_EIM_D21__GPIO2_5 = IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
54 MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
55 MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
56 MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
[all …]
/openbmc/linux/drivers/net/ethernet/cavium/thunder/
H A Dthunder_bgx.h10 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026
11 #define PCI_DEVICE_ID_THUNDER_RGX 0xA054
14 #define PCI_SUBSYS_DEVID_88XX_BGX 0xA126
15 #define PCI_SUBSYS_DEVID_81XX_BGX 0xA226
16 #define PCI_SUBSYS_DEVID_81XX_RGX 0xA254
17 #define PCI_SUBSYS_DEVID_83XX_BGX 0xA326
27 #define DEFAULT_PAUSE_TIME 0xFFFF
29 #define BGX_ID_MASK 0x3
30 #define LMAC_ID_MASK 0x3
35 #define BGX_CMRX_CFG 0x00
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h11 #define CONFIG_SYS_IMMR 0x01000000
12 #define CONFIG_SYS_DCSRBAR 0x20000000
13 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
14 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
17 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
18 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
19 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
[all …]
/openbmc/linux/drivers/net/dsa/sja1105/
H A Dsja1105_spi.c21 memset(buf, 0, size); in sja1105_spi_message_pack()
38 u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER] = {0}; in sja1105_xfer()
40 struct spi_transfer xfers[2] = {0}; in sja1105_xfer()
45 int rc, i = 0; in sja1105_xfer()
53 hdr_xfer = &xfers[0]; in sja1105_xfer()
56 for (i = 0; i < num_chunks; i++) { in sja1105_xfer()
67 msg.read_count = 0; in sja1105_xfer()
106 if (rc < 0) { in sja1105_xfer()
112 return 0; in sja1105_xfer()
139 sja1105_pack(packed_buf, value, 63, 0, 8); in sja1105_xfer_u64()
[all …]
/openbmc/u-boot/include/
H A Dtsi148.h14 #define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148
23 unsigned int otsau; /* 0x000 Outbound start upper */
24 unsigned int otsal; /* 0x004 Outbouud start lower */
25 unsigned int oteau; /* 0x008 Outbound end upper */
26 unsigned int oteal; /* 0x00c Outbound end lower */
27 unsigned int otofu; /* 0x010 Outbound translation upper */
28 unsigned int otofl; /* 0x014 Outbound translation lower */
29 unsigned int otbs; /* 0x018 Outbound translation 2eSST */
30 unsigned int otat; /* 0x01c Outbound translation attr */
34 unsigned int itsau; /* 0x000 inbound start upper */
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Ddenali.h14 #define DEVICE_RESET 0x0
17 #define TRANSFER_SPARE_REG 0x10
18 #define TRANSFER_SPARE_REG__FLAG BIT(0)
20 #define LOAD_WAIT_CNT 0x20
21 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
23 #define PROGRAM_WAIT_CNT 0x30
24 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
26 #define ERASE_WAIT_CNT 0x40
27 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
29 #define INT_MON_CYCCNT 0x50
[all …]

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