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/openbmc/linux/scripts/
H A Dextract_xc3028.pl25 my $debug=0;
50 while ($length > 0) {
66 my $msb = ($val >> 8) &0xff;
67 my $lsb = $val & 0xff;
75 my $l3 = ($val >> 24) & 0xff;
76 my $l2 = ($val >> 16) & 0xff;
77 my $l1 = ($val >> 8) & 0xff;
78 my $l0 = $val & 0xff;
87 my $l7 = ($msb_val >> 24) & 0xff;
88 my $l6 = ($msb_val >> 16) & 0xff;
[all …]
/openbmc/u-boot/include/configs/
H A Drk3188_common.h21 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
23 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
24 #define CONFIG_SYS_LOAD_ADDR 0x60800800
26 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
29 #define CONFIG_SPL_TEXT_BASE 0x10080800
31 #define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
34 #define CONFIG_SPL_STACK 0x10087fff
36 #define CONFIG_SYS_SDRAM_BASE 0x60000000
38 #define SDRAM_MAX_SIZE 0x80000000
45 "scriptaddr=0x60000000\0" \
[all …]
H A Drv1108_common.h17 #define CONFIG_SYS_TIMER_BASE 0x10350020
20 #define CONFIG_SYS_SDRAM_BASE 0x60000000
21 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
22 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
31 "scriptaddr=0x60000000\0" \
32 "fdt_addr_r=0x61f00000\0" \
33 "kernel_addr_r=0x62000000\0" \
34 "ramdisk_addr_r=0x64000000\0"
39 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
H A Drk3036_common.h16 #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
19 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
20 #define CONFIG_SYS_LOAD_ADDR 0x60800800
21 #define CONFIG_SPL_STACK 0x10081fff
22 #define CONFIG_SPL_TEXT_BASE 0x10081000
27 #define CONFIG_SYS_SDRAM_BASE 0x60000000
41 "scriptaddr=0x60000000\0" \
42 "pxefile_addr_r=0x60100000\0" \
43 "fdt_addr_r=0x61f00000\0" \
44 "kernel_addr_r=0x62000000\0" \
[all …]
H A Drk322x_common.h17 #define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
20 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
21 #define CONFIG_SYS_LOAD_ADDR 0x60800800
22 #define CONFIG_SPL_STACK 0x10088000
23 #define CONFIG_SPL_TEXT_BASE 0x10081000
28 #define CONFIG_SYS_SDRAM_BASE 0x60000000
30 #define SDRAM_MAX_SIZE 0x80000000
40 "scriptaddr=0x60000000\0" \
41 "pxefile_addr_r=0x60100000\0" \
42 "fdt_addr_r=0x61f00000\0" \
[all …]
H A Dedb93xx.h38 #define CONFIG_ENV_SECT_SIZE 0x00020000
42 #define CONFIG_ENV_SECT_SIZE 0x00020000
46 #define CONFIG_ENV_SECT_SIZE 0x00020000
50 #define CONFIG_ENV_SECT_SIZE 0x00040000
54 #define CONFIG_ENV_SECT_SIZE 0x00020000
58 #define CONFIG_ENV_SECT_SIZE 0x00040000
62 #define CONFIG_ENV_SECT_SIZE 0x00040000
66 #define CONFIG_ENV_SECT_SIZE 0x00020000
83 #define CONFIG_SYS_SERIAL0 0x808C0000
84 #define CONFIG_SYS_SERIAL1 0x808D0000
[all …]
H A Dve8313.h33 #define CONFIG_SYS_IMMR 0xE0000000
35 #define CONFIG_SYS_MEMTEST_START 0x00001000
36 #define CONFIG_SYS_MEMTEST_END 0x07000000
48 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
63 /* 0x80840102 */
65 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
66 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
67 | (0 << TIMING_CFG0_WRT_SHIFT) \
74 /* 0x0e720802 */
83 /* 0x26256222 */
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear300.dtsi15 ranges = <0x60000000 0x60000000 0x50000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0x99000000 0x1000>;
25 reg = <0x60000000 0x1000>;
34 reg = <0x94000000 0x1000 /* FSMC Register */
35 0x80000000 0x0010 /* NAND Base DATA */
36 0x80020000 0x0010 /* NAND Base ADDR */
37 0x80010000 0x0010>; /* NAND Base CMD */
44 reg = <0x70000000 0x100>;
51 reg = <0x50000000 0x1000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsp9860g-1h10.dts29 reg = <0x0 0x80000000 0 0x60000000>,
30 <0x1 0x80000000 0 0x60000000>;
50 ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>,
56 <3680000 10>, <3605000 5>, <3400000 0>;
/openbmc/u-boot/doc/device-tree-bindings/memory/
H A Dmemory.txt14 - #size-cells: should be 0.
40 reg = <0x20000000 0x20000000
41 0x40000000 0x20000000
42 0x60000000 0x20000000
43 0x80000000 0x20000000>;
45 board-id@0 {
47 reg = <0x20000000 0x20000000
48 0x40000000 0x20000000>;
53 reg = <0x20000000 0x20000000
54 0x40000000 0x20000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxlnx,axi-pcie-host.yaml41 const: 0
71 reg = <0x50000000 0x1000000>;
77 interrupt-map-mask = <0 0 0 7>;
78 interrupt-map = <0 0 0 1 &pcie_intc 1>,
79 <0 0 0 2 &pcie_intc 2>,
80 <0 0 0 3 &pcie_intc 3>,
81 <0 0 0 4 &pcie_intc 4>;
82 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>;
85 #address-cells = <0>;
H A Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
H A Dmediatek,mt7621-pcie.yaml26 - description: pcie port 0 RC control registers
34 '^pcie@[0-2],0$':
49 pattern: '^pcie-phy[0-2]$'
81 reg = <0x1e140000 0x100>,
82 <0x1e142000 0x100>,
83 <0x1e143000 0x100>,
84 <0x1e144000 0x100>;
89 pinctrl-0 = <&pcie_pins>;
91 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
92 <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dcontregs.h15 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
16 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
17 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
18 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
19 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
20 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
21 #define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
22 #define AC_SYNC_ERR 0x60000000 /* c fault type */
23 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
24 #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
[all …]
H A Dsun3mmu.h25 #define SUN3_CONTROL_MASK (0x0FFFFFFC)
29 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
30 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
31 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
32 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
33 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
34 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
35 #define AC_BUS_ERROR 0x60000000 /* 34 Cleared on read, byte. */
36 #define AC_SYNC_ERR 0x60000000 /* c fault type */
37 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
/openbmc/linux/arch/mips/pci/
H A Dpci-rc32434.c36 #define PCI_ACCESS_READ 0
53 .start = 0x50000000,
54 .end = 0x5FFFFFFF,
62 .start = 0x60000000,
63 .end = 0x6FFFFFFF,
72 .start = 0x18800000,
73 .end = 0x188FFFFF,
97 .mem_offset = 0,
98 .io_offset = 0,
105 #define PCI_ENDIAN_FLAG 0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2e.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
57 reg = <0x2620750 24>;
65 reg = <0x25000000 0x10000>;
76 reg = <0x25010000 0x70000>;
86 gpio,syscon-dev = <&devctrl 0x240>;
95 reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
96 ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
97 0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
[all …]
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h164 * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
167 #define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
168 #define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
169 #define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
177 #define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
179 #define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
183 #define XCHAL_ITLB_WAY0_SET 0
186 #define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
189 #define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
192 /* ITLB way set 0 (group of ways 0 thru 0): */
[all …]
/openbmc/linux/arch/x86/realmode/rm/
H A Dreboot.S17 * This code is called with the restart type (0 = BIOS, 1 = APM) in
87 * actual BIOS entry point, anyway (that is at 0xfffffff0).
99 andl $0x00000011, %edx
100 orl $0x60000000, %edx
104 testl $0x60000000, %edx /* If no cache bits -> no wbinvd */
108 andb $0x10, %dl
116 movw $0x1000, %ax
118 movw $0xf000, %sp
119 movw $0x5307, %ax
120 movw $0x0001, %bx
[all …]
/openbmc/linux/arch/sh/include/cpu-sh2a/cpu/
H A Daddrspace.h5 #define P0SEG 0x00000000
6 #define P1SEG 0x00000000
7 #define P2SEG 0x20000000
8 #define P3SEG 0x40000000
9 #define P4SEG 0x60000000
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am64.dtsi53 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
57 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
58 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
59 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
60 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
62 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
/openbmc/linux/arch/arm/boot/dts/cirrus/
H A Dep7209.dtsi28 #address-cells = <0>;
29 #size-cells = <0>;
47 reg = <0x80000000 0xc000>;
53 reg = <0x80000000 0x4000>;
60 reg = <0x80000000 0x1 0x80000040 0x1>;
67 reg = <0x80000001 0x1 0x80000041 0x1>;
74 reg = <0x80000003 0x1 0x80000043 0x1>;
81 reg = <0x80000083 0x1 0x800000c3 0x1>;
88 reg = <0x80000100 0x80>;
96 reg = <0x80000180 0x80>;
[all …]
/openbmc/openbmc/meta-arm/meta-arm/recipes-bsp/u-boot/u-boot/
H A Dqemuarm64.cfg3 CONFIG_SYS_TEXT_BASE=0x60000000

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