Lines Matching +full:0 +full:x60000000
33 #define CONFIG_SYS_IMMR 0xE0000000
35 #define CONFIG_SYS_MEMTEST_START 0x00001000
36 #define CONFIG_SYS_MEMTEST_END 0x07000000
48 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
63 /* 0x80840102 */
65 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
66 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
67 | (0 << TIMING_CFG0_WRT_SHIFT) \
74 /* 0x0e720802 */
83 /* 0x26256222 */
84 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
91 /* 0x029028c7 */
92 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
93 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
94 /* 0x03202000 */
98 /* 0x43080000 */
99 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
100 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
101 | (0x0232 << SDRAM_MODE_SD_SHIFT))
102 /* 0x44400232 */
103 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
106 /*0x02000000*/
111 /* 0x73000002 */
116 #define CONFIG_SYS_FLASH_BASE 0xFE000000
130 /* 0xfe000c55 */
148 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
149 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
165 #define CONFIG_SYS_LBC_LBCR 0x00040000
167 #define CONFIG_SYS_LBC_MRTPR 0x20000000
172 #define CONFIG_SYS_NAND_BASE 0x61000000
182 /* 0x61000c21 */
189 /* 0xffff90ac */
203 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \
206 /* 0x60000801 */
214 /* 0xfffe0937 */
215 /* local bus read write buffer mapping SRAM@0x64000000 */
216 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \
219 /* 0x62001001 */
228 /* 0xfe0009f7 */
235 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
240 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
241 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
248 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
250 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
251 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
253 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
254 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
255 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
256 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
258 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
269 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
270 #define TSEC1_PHY_ADDR 0x01
271 #define TSEC1_FLAGS 0
272 #define TSEC1_PHYIDX 0
275 /* Options are: TSEC[0-1] */
283 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
284 #define CONFIG_ENV_SIZE 0x4000
305 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
318 /* 0x64050000 */
320 0x20000000 /* reserved, must be set */ |\
325 /* 0xa0600004 */
338 #define CONFIG_SYS_SICRH (0x01000000 | \
347 /* 0x010fff03 */
354 /* 0x33fc0003) */
356 #define CONFIG_SYS_HID0_INIT 0x000000000
364 /* DDR @ 0x00000000 */
372 /* PCI @ 0x80000000 */
387 #define CONFIG_SYS_IBAT1L (0)
388 #define CONFIG_SYS_IBAT1U (0)
389 #define CONFIG_SYS_IBAT2L (0)
390 #define CONFIG_SYS_IBAT2U (0)
394 #define CONFIG_SYS_IBAT3L (0)
395 #define CONFIG_SYS_IBAT3U (0)
396 #define CONFIG_SYS_IBAT4L (0)
397 #define CONFIG_SYS_IBAT4U (0)
399 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
409 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
410 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
411 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
413 /* FPGA, SRAM, NAND @ 0x60000000 */
414 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
415 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
440 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
441 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
442 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
443 "u-boot_addr_r=100000\0" \
444 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
450 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \