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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-ddr.dtsi11 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
15 reg = <0x5c020000 0x10000>;
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dsram.yaml159 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
163 ranges = <0 0x5c000000 0x40000>;
166 reg = <0x100 0x50>;
170 reg = <0x1000 0x1000>;
175 reg = <0x20000 0x20000>;
190 reg = <0x02020000 0x54000>;
193 ranges = <0 0x02020000 0x54000>;
195 smp-sram@0 {
197 reg = <0x0 0x1000>;
202 reg = <0x53000 0x1000>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Demac_defs.h24 #define EMAC_BASE_ADDR 0x5C010000
25 #define EMAC_WRAPPER_BASE_ADDR 0x5C000000
26 #define EMAC_WRAPPER_RAM_ADDR 0x5C020000
27 #define EMAC_MDIO_BASE_ADDR 0x5C030000
28 #define EMAC_HW_RAM_ADDR 0x01E20000
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dti_qspi.txt23 parameters for Mode-0 and Mode-3 operations, which needs to be set up by
24 the bootloader (U-Boot). Default configuration only supports Mode-0
34 reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
37 #size-cells = <0>;
45 reg = <0x4b300000 0x100>,
46 <0x5c000000 0x4000000>,
48 syscon-chipselects = <&scm_conf 0x558>;
50 #size-cells = <0>;
/openbmc/linux/arch/arm/mach-omap2/
H A Domap24xx.h19 #define L4_24XX_BASE 0x48000000
20 #define L4_WK_243X_BASE 0x49000000
21 #define L3_24XX_BASE 0x68000000
24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
25 #define OMAP24XX_IVA_INTC_BASE 0x40000000
28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
33 #define OMAP2420_SMS_BASE 0x68008000
[all …]
H A Dpdata-quirks.c48 omap_auxdata_lookup[0].platform_data = n8x0_legacy_init(); in omap2420_n8x0_legacy_init()
111 gpiod_export(d, 0); in omap3_sbc_t3x_usb_hub_init()
114 gpiod_set_value(d, 0); in omap3_sbc_t3x_usb_hub_init()
121 GPIO_LOOKUP_IDX("gpio-160-175", 7, "reset", 0,
130 omap3_sbc_t3x_usb_hub_init("sb-t35 usb hub", 0); in omap3_sbc_t3730_legacy_init()
136 omap3_sbc_t3x_usb_hub_init("sb-t35 usb hub", 0); in omap3_sbc_t3530_legacy_init()
185 GPIO_LOOKUP("gpio-0-15", 4, "noe",
203 gpiod_export(d, 0); in omap3_sbc_t3517_wifi_init()
211 gpiod_export(d, 0); in omap3_sbc_t3517_wifi_init()
214 gpiod_set_value(d, 0); in omap3_sbc_t3517_wifi_init()
[all …]
/openbmc/u-boot/arch/arm/mach-stm32mp/include/mach/
H A Dstm32.h13 #define STM32_RCC_BASE 0x50000000
14 #define STM32_PWR_BASE 0x50001000
15 #define STM32_DBGMCU_BASE 0x50081000
16 #define STM32_BSEC_BASE 0x5C005000
17 #define STM32_TZC_BASE 0x5C006000
18 #define STM32_ETZPC_BASE 0x5C007000
19 #define STM32_TAMP_BASE 0x5C00A000
23 #define STM32_USART1_BASE 0x5C000000
24 #define STM32_USART2_BASE 0x4000E000
25 #define STM32_USART3_BASE 0x4000F000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam3517.dtsi24 reg = <0x5c040000 0x1000>;
33 reg = <0x5c000000 0x30000>;
36 ti,davinci-ctrl-reg-offset = <0x10000>;
37 ti,davinci-ctrl-mod-reg-offset = <0>;
38 ti,davinci-ctrl-ram-offset = <0x20000>;
39 ti,davinci-ctrl-ram-size = <0x2000>;
50 reg = <0x5c030000 0x1000>;
53 #size-cells = <0>;
62 reg = <0x4809e000 0x400>;
71 reg = <0x480025d8 0x24>;
[all …]
H A Dstm32mp157c.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
64 reg = <0xa0021000 0x1000>,
65 <0xa0022000 0x2000>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
91 #clock-cells = <0>;
[all …]
/openbmc/u-boot/include/configs/
H A Dzipitz2.h23 #define CONFIG_ENV_ADDR 0x40000
24 #define CONFIG_ENV_SIZE 0x10000
30 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
32 "source 0xa0000000; " \
34 "bootm 0x50000; " \
55 #define CONFIG_SYS_MMC_BASE 0xF0000000
83 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=System…
88 #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
89 #define PHYS_SRAM_SIZE 0x00040000 /* 256k */
94 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-opp-vesnin.dts18 reg = <0x40000000 0x20000000>;
28 reg = <0x5f000000 0x01000000>; /* 16MB */
32 reg = <0x5c000000 0x02000000>; /* 32M */
51 gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>;
82 flash@0 {
99 pinctrl-0 = <&pinctrl_spi1debug_default>;
101 flash@0 {
112 pinctrl-0 = <&pinctrl_rmii1_default>;
133 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
141 reg = <0x50>;
[all …]
H A Daspeed-bmc-opp-palmetto.dts17 reg = <0x40000000 0x20000000>;
27 reg = <0x5f000000 0x01000000>; /* 16M */
31 reg = <0x5ee00000 0x00200000>;
37 reg = <0x5C000000 0x02000000>; /* 32MB */
60 #size-cells = <0>;
69 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
86 flash@0 {
98 pinctrl-0 = <&pinctrl_spi1debug_default>;
100 flash@0 {
110 pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6115-fxtec-pro1x.dts17 qcom,msm-id = <QCOM_ID_SM6115 0x10000>;
26 reg = <0x0 0x5c000000 0x0 (1080 * 2160 * 4)>;
38 pinctrl-0 = <&vol_up_n>;
61 power-source = <0>;
77 regulators-0 {
214 gpio-reserved-ranges = <0 4>, <14 4>;
H A Dsm4250-oneplus-billie2.dts15 qcom,msm-id = <0x1a1 0x10000 0x1bc 0x10000>;
16 qcom,board-id = <0x1000b 0x00>;
30 reg = <0 0x5c000000 0 (1600 * 720 * 4)>;
41 reg = <0x0 0x5fff7000 0x0 0x8000>;
47 reg = <0x0 0xcbe00000 0x0 0x400000>;
48 record-size = <0x40000>;
49 pmsg-size = <0x200000>;
50 console-size = <0x40000>;
51 ftrace-size = <0x40000>;
55 reg = <0x0 0xcc200000 0x0 0x100000>;
[all …]
H A Dsm6115p-lenovo-j606f.dts17 qcom,msm-id = <445 0x10000>, <420 0x10000>;
31 reg = <0 0x5c000000 0 (2000 * 1200 * 4)>;
44 pinctrl-0 = <&vol_up_n>;
59 reg = <0x0 0xffc00000 0x0 0x100000>;
60 record-size = <0x1000>;
61 console-size = <0x40000>;
62 ftrace-size = <0x20000>;
84 panel: panel@0 {
86 reg = <0>;
92 pinctrl-0 = <&te_active &mdss_dsi_active>;
[all …]
H A Dsm6125-xiaomi-laurel-sprout.dts21 qcom,msm-id = <394 0>; /* sm6125 v1 */
22 qcom,board-id = <11 0>;
31 reg = <0 0x5c000000 0 (1560 * 720 * 4)>;
41 reg = <0x0 0xffb00000 0x0 0xc0000>;
46 reg = <0x0 0xffbc0000 0x0 0x80000>;
52 reg = <0x0 0xffc40000 0x0 0xc0000>;
53 record-size = <0x1000>;
54 console-size = <0x40000>;
55 pmsg-size = <0x20000>;
59 reg = <0x0 0xffd40000 0x0 0x1000>;
[all …]
H A Dsm6125-sony-xperia-seine-pdx201.dts16 qcom,msm-id = <394 0x10000>; /* sm6125 v1 */
17 qcom,board-id = <34 0>;
35 reg = <0 0x5c000000 0 (2520 * 1080 * 4)>;
51 pinctrl-0 = <&vol_down_n>;
68 reg = <0x0 0xffb00000 0x0 0xc0000>;
73 reg = <0x0 0xffbc0000 0x0 0x80000>;
79 reg = <0x0 0xffc40000 0x0 0xc0000>;
80 record-size = <0x1000>;
81 console-size = <0x40000>;
82 pmsg-size = <0x20000>;
[all …]
H A Dsm6125.dtsi23 #clock-cells = <0>;
30 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
57 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
75 reg = <0x0 0x3>;
84 reg = <0x0 0x100>;
98 reg = <0x0 0x101>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam3517.dtsi21 cpu: cpu@0 {
41 opp-supported-hw = <0xffffffff 0xffffffff>;
49 opp-supported-hw = <0xffffffff 0xffffffff>;
56 reg = <0x5c040400 0x4>,
57 <0x5c040404 0x4>,
58 <0x5c040408 0x4>;
74 ranges = <0x0 0x5c040000 0x1000>;
76 am35x_otg_hs: am35x_otg_hs@0 {
79 reg = <0 0x1000>;
89 reg = <0x5c000000 0x30000>;
[all …]
H A Ddra7.dtsi61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0>;
109 opp-supported-hw = <0xFF 0x01>;
119 opp-supported-hw = <0xFF 0x02>;
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h9 #define BIT_C 0x00000001
11 #define OP_BLR 0x4e800020
12 #define OP_EXTSB 0x7c000774
13 #define OP_EXTSH 0x7c000734
14 #define OP_NEG 0x7c0000d0
15 #define OP_CNTLZW 0x7c000034
16 #define OP_ADD 0x7c000214
17 #define OP_ADDC 0x7c000014
18 #define OP_ADDME 0x7c0001d4
19 #define OP_ADDZE 0x7c000194
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa3xx.c51 #define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0))
61 #define ISRAM_START 0x5c000000
77 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); in pxa3xx_cpu_standby()
79 memcpy_toio(sram + 0x8000, pm_enter_standby_start, in pxa3xx_cpu_standby()
82 AD2D0SR = ~0; in pxa3xx_cpu_standby()
83 AD2D1SR = ~0; in pxa3xx_cpu_standby()
85 AD2D1ER = 0; in pxa3xx_cpu_standby()
93 AD2D0ER = 0; in pxa3xx_cpu_standby()
94 AD2D1ER = 0; in pxa3xx_cpu_standby()
102 * 0x5c014000 for the moment.
[all …]
/openbmc/qemu/hw/arm/
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
54 0x33b,
55 0x33b,
56 0x769,
57 0x76d
68 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
70 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
71 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
93 int is_mpcore = 0; in realview_init()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dti_qspi.c33 #define QSPI_CLK_DIV_MAX 0xffff
49 #define QSPI_BUSY BIT(0)
52 #define MM_SWITCH 0x01
54 #define MEM_CS_UNSELECT 0xfffff8ff
55 #define MMAP_START_ADDR_DRA 0x5c000000
56 #define MMAP_START_ADDR_AM43x 0x30000000
57 #define CORE_CTRL_IO 0x4a002558
59 #define QSPI_CMD_READ (0x3 << 0)
60 #define QSPI_CMD_READ_DUAL (0x6b << 0)
61 #define QSPI_CMD_READ_QUAD (0x6c << 0)
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]

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