xref: /openbmc/linux/arch/arm/boot/dts/ti/omap/am3517.dtsi (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)
1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only
2724ba675SRob Herring/*
3724ba675SRob Herring * Device Tree Source for am3517 SoC
4724ba675SRob Herring *
5724ba675SRob Herring * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
6724ba675SRob Herring */
7724ba675SRob Herring
8724ba675SRob Herring#include "omap3.dtsi"
9724ba675SRob Herring
10724ba675SRob Herring/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */
11724ba675SRob Herring/delete-node/ &aes1_target;
12724ba675SRob Herring/delete-node/ &aes2_target;
13724ba675SRob Herring
14724ba675SRob Herring/ {
15724ba675SRob Herring	aliases {
16724ba675SRob Herring		serial3 = &uart4;
17724ba675SRob Herring		can = &hecc;
18724ba675SRob Herring	};
19724ba675SRob Herring
20724ba675SRob Herring	cpus {
21724ba675SRob Herring		cpu: cpu@0 {
22724ba675SRob Herring			/* Based on OMAP3630 variants OPP50 and OPP100 */
23724ba675SRob Herring			operating-points-v2 = <&cpu0_opp_table>;
24724ba675SRob Herring
25724ba675SRob Herring			clock-latency = <300000>; /* From legacy driver */
26724ba675SRob Herring		};
27724ba675SRob Herring	};
28724ba675SRob Herring
29724ba675SRob Herring	cpu0_opp_table: opp-table {
30724ba675SRob Herring		compatible = "operating-points-v2-ti-cpu";
31724ba675SRob Herring		syscon = <&scm_conf>;
32724ba675SRob Herring		/*
33724ba675SRob Herring		 * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx
34724ba675SRob Herring		 * appear to operate at 300MHz as well. Since AM3517 only
35724ba675SRob Herring		 * lists one operating voltage, it will remain fixed at 1.2V
36724ba675SRob Herring		 */
37*5821d766SNishanth Menon		opp-50-300000000 {
38*5821d766SNishanth Menon			/* OPP50 */
39724ba675SRob Herring			opp-hz = /bits/ 64 <300000000>;
40724ba675SRob Herring			opp-microvolt = <1200000>;
41724ba675SRob Herring			opp-supported-hw = <0xffffffff 0xffffffff>;
42724ba675SRob Herring			opp-suspend;
43724ba675SRob Herring		};
44724ba675SRob Herring
45*5821d766SNishanth Menon		opp-100-600000000 {
46*5821d766SNishanth Menon			/* OPP100 */
47724ba675SRob Herring			opp-hz = /bits/ 64 <600000000>;
48724ba675SRob Herring			opp-microvolt = <1200000>;
49724ba675SRob Herring			opp-supported-hw = <0xffffffff 0xffffffff>;
50724ba675SRob Herring		};
51724ba675SRob Herring	};
52724ba675SRob Herring
53724ba675SRob Herring	ocp@68000000 {
54724ba675SRob Herring		target-module@5c040000 {
55724ba675SRob Herring			compatible = "ti,sysc-omap2", "ti,sysc";
56724ba675SRob Herring			reg = <0x5c040400 0x4>,
57724ba675SRob Herring			      <0x5c040404 0x4>,
58724ba675SRob Herring			      <0x5c040408 0x4>;
59724ba675SRob Herring			reg-names = "rev", "sysc", "syss";
60724ba675SRob Herring			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
61724ba675SRob Herring					 SYSC_OMAP2_SOFTRESET |
62724ba675SRob Herring					 SYSC_OMAP2_AUTOIDLE)>;
63724ba675SRob Herring			ti,sysc-midle = <SYSC_IDLE_FORCE>,
64724ba675SRob Herring					<SYSC_IDLE_NO>,
65724ba675SRob Herring					<SYSC_IDLE_SMART>;
66724ba675SRob Herring			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
67724ba675SRob Herring					<SYSC_IDLE_NO>,
68724ba675SRob Herring					<SYSC_IDLE_SMART>;
69724ba675SRob Herring			ti,syss-mask = <1>;
70724ba675SRob Herring			clocks = <&hsotgusb_ick_am35xx>;
71724ba675SRob Herring			clock-names = "fck";
72724ba675SRob Herring			#address-cells = <1>;
73724ba675SRob Herring			#size-cells = <1>;
74724ba675SRob Herring			ranges = <0x0 0x5c040000 0x1000>;
75724ba675SRob Herring
76724ba675SRob Herring			am35x_otg_hs: am35x_otg_hs@0 {
77724ba675SRob Herring				compatible = "ti,omap3-musb";
78724ba675SRob Herring				status = "disabled";
79724ba675SRob Herring				reg = <0 0x1000>;
80724ba675SRob Herring				interrupts = <71>;
81724ba675SRob Herring				interrupt-names = "mc";
82724ba675SRob Herring			};
83724ba675SRob Herring		};
84724ba675SRob Herring
85724ba675SRob Herring		davinci_emac: ethernet@5c000000 {
86724ba675SRob Herring			compatible = "ti,am3517-emac";
87724ba675SRob Herring			ti,hwmods = "davinci_emac";
88724ba675SRob Herring			status = "disabled";
89724ba675SRob Herring			reg = <0x5c000000 0x30000>;
90724ba675SRob Herring			interrupts = <67 68 69 70>;
91724ba675SRob Herring			syscon = <&scm_conf>;
92724ba675SRob Herring			ti,davinci-ctrl-reg-offset = <0x10000>;
93724ba675SRob Herring			ti,davinci-ctrl-mod-reg-offset = <0>;
94724ba675SRob Herring			ti,davinci-ctrl-ram-offset = <0x20000>;
95724ba675SRob Herring			ti,davinci-ctrl-ram-size = <0x2000>;
96724ba675SRob Herring			ti,davinci-rmii-en = /bits/ 8 <1>;
97724ba675SRob Herring			local-mac-address = [ 00 00 00 00 00 00 ];
98724ba675SRob Herring			clocks = <&emac_ick>;
99724ba675SRob Herring			clock-names = "ick";
100724ba675SRob Herring		};
101724ba675SRob Herring
102724ba675SRob Herring		davinci_mdio: mdio@5c030000 {
103724ba675SRob Herring			compatible = "ti,davinci_mdio";
104724ba675SRob Herring			ti,hwmods = "davinci_mdio";
105724ba675SRob Herring			status = "disabled";
106724ba675SRob Herring			reg = <0x5c030000 0x1000>;
107724ba675SRob Herring			bus_freq = <1000000>;
108724ba675SRob Herring			#address-cells = <1>;
109724ba675SRob Herring			#size-cells = <0>;
110724ba675SRob Herring			clocks = <&emac_fck>;
111724ba675SRob Herring			clock-names = "fck";
112724ba675SRob Herring		};
113724ba675SRob Herring
114724ba675SRob Herring		uart4: serial@4809e000 {
115724ba675SRob Herring			compatible = "ti,omap3-uart";
116724ba675SRob Herring			ti,hwmods = "uart4";
117724ba675SRob Herring			status = "disabled";
118724ba675SRob Herring			reg = <0x4809e000 0x400>;
119724ba675SRob Herring			interrupts = <84>;
120724ba675SRob Herring			dmas = <&sdma 55 &sdma 54>;
121724ba675SRob Herring			dma-names = "tx", "rx";
122724ba675SRob Herring			clock-frequency = <48000000>;
123724ba675SRob Herring		};
124724ba675SRob Herring
125724ba675SRob Herring		omap3_pmx_core2: pinmux@480025d8 {
126724ba675SRob Herring			compatible = "ti,omap3-padconf", "pinctrl-single";
127724ba675SRob Herring			reg = <0x480025d8 0x24>;
128724ba675SRob Herring			#address-cells = <1>;
129724ba675SRob Herring			#size-cells = <0>;
130724ba675SRob Herring			#pinctrl-cells = <1>;
131724ba675SRob Herring			#interrupt-cells = <1>;
132724ba675SRob Herring			interrupt-controller;
133724ba675SRob Herring			pinctrl-single,register-width = <16>;
134724ba675SRob Herring			pinctrl-single,function-mask = <0xff1f>;
135724ba675SRob Herring		};
136724ba675SRob Herring
137724ba675SRob Herring		hecc: can@5c050000 {
138724ba675SRob Herring			compatible = "ti,am3517-hecc";
139724ba675SRob Herring			status = "disabled";
140724ba675SRob Herring			reg = <0x5c050000 0x80>,
141724ba675SRob Herring			      <0x5c053000 0x180>,
142724ba675SRob Herring			      <0x5c052000 0x200>;
143724ba675SRob Herring			reg-names = "hecc", "hecc-ram", "mbx";
144724ba675SRob Herring			interrupts = <24>;
145724ba675SRob Herring			clocks = <&hecc_ck>;
146724ba675SRob Herring		};
147724ba675SRob Herring
148724ba675SRob Herring		/*
149724ba675SRob Herring		 * On am3517 the OCP registers do not seem to be accessible
150724ba675SRob Herring		 * similar to the omap34xx. Maybe SGX is permanently set to
151724ba675SRob Herring		 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
152724ba675SRob Herring		 * write-only at 0x50000e10. We detect SGX based on the SGX
153724ba675SRob Herring		 * revision register instead of the unreadable OCP revision
154724ba675SRob Herring		 * register.
155724ba675SRob Herring		 */
156724ba675SRob Herring		sgx_module: target-module@50000000 {
157724ba675SRob Herring			compatible = "ti,sysc-omap2", "ti,sysc";
158724ba675SRob Herring			reg = <0x50000014 0x4>;
159724ba675SRob Herring			reg-names = "rev";
160724ba675SRob Herring			clocks = <&sgx_fck>, <&sgx_ick>;
161724ba675SRob Herring			clock-names = "fck", "ick";
162724ba675SRob Herring			#address-cells = <1>;
163724ba675SRob Herring			#size-cells = <1>;
164724ba675SRob Herring			ranges = <0 0x50000000 0x4000>;
165724ba675SRob Herring
166724ba675SRob Herring			/*
167724ba675SRob Herring			 * Closed source PowerVR driver, no child device
168724ba675SRob Herring			 * binding or driver in mainline
169724ba675SRob Herring			 */
170724ba675SRob Herring		};
171724ba675SRob Herring	};
172724ba675SRob Herring};
173724ba675SRob Herring
174724ba675SRob Herring/* Not currently working, probably needs at least different clocks */
175724ba675SRob Herring&rng_target {
176724ba675SRob Herring	status = "disabled";
177724ba675SRob Herring	/delete-property/ clocks;
178724ba675SRob Herring};
179724ba675SRob Herring
180724ba675SRob Herring/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
181724ba675SRob Herring&usb_otg_target {
182724ba675SRob Herring	status = "disabled";
183724ba675SRob Herring};
184724ba675SRob Herring
185724ba675SRob Herring&iva {
186724ba675SRob Herring	status = "disabled";
187724ba675SRob Herring};
188724ba675SRob Herring
189724ba675SRob Herring&mailbox {
190724ba675SRob Herring	status = "disabled";
191724ba675SRob Herring};
192724ba675SRob Herring
193724ba675SRob Herring&mmu_isp {
194724ba675SRob Herring	status = "disabled";
195724ba675SRob Herring};
196724ba675SRob Herring
197724ba675SRob Herring#include "am35xx-clocks.dtsi"
198724ba675SRob Herring#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
199724ba675SRob Herring
200724ba675SRob Herring/* Preferred always-on timer for clocksource */
201724ba675SRob Herring&timer1_target {
202724ba675SRob Herring	ti,no-reset-on-init;
203724ba675SRob Herring	ti,no-idle;
204724ba675SRob Herring	timer@0 {
205724ba675SRob Herring		assigned-clocks = <&gpt1_fck>;
206724ba675SRob Herring		assigned-clock-parents = <&sys_ck>;
207724ba675SRob Herring	};
208724ba675SRob Herring};
209724ba675SRob Herring
210724ba675SRob Herring/* Preferred timer for clockevent */
211724ba675SRob Herring&timer2_target {
212724ba675SRob Herring	ti,no-reset-on-init;
213724ba675SRob Herring	ti,no-idle;
214724ba675SRob Herring	timer@0 {
215724ba675SRob Herring		assigned-clocks = <&gpt2_fck>;
216724ba675SRob Herring		assigned-clock-parents = <&sys_ck>;
217724ba675SRob Herring	};
218724ba675SRob Herring};
219