/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8-ss-img.dtsi | 10 ranges = <0x58000000 0x0 0x58000000 0x1000000>; 14 #clock-cells = <0>; 20 reg = <0x58400000 0x00050000>; 39 reg = <0x58450000 0x00050000>; 59 reg = <0x585d0000 0x10000>; 71 reg = <0x585f0000 0x10000>;
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/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | faraday,ftpci100.yaml | 18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday 19 Technology) and product ID 0x4321. 34 interrupt-map-mask = <0xf800 0 0 7>; 36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 37 <0x4800 0 0 2 &pci_intc 1>, 38 <0x4800 0 0 3 &pci_intc 2>, 39 <0x4800 0 0 4 &pci_intc 3>, 40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 41 <0x5000 0 0 2 &pci_intc 2>, 42 <0x5000 0 0 3 &pci_intc 3>, [all …]
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H A D | nvidia,tegra20-pcie.txt | 27 - cell 0 specifies the bus and device numbers of the root port: 30 - cell 1 denotes the upper 32 address bits and should be 0 45 - 0x81000000: I/O memory region 46 - 0x82000000: non-prefetchable memory region 47 - 0xc2000000: prefetchable memory region 73 - pinctrl-0: phandle for the default/active state of pin configurations. 104 - If lanes 0 to 3 are used: 150 - Root port 0 uses 4 lanes, root port 1 is unused. 158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes. 171 reg = <0x80003000 0x00000800 /* PADS registers */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/gpu/ |
H A D | nvidia,gk20a.txt | 46 reg = <0x0 0x57000000 0x0 0x01000000>, 47 <0x0 0x58000000 0x0 0x01000000>; 64 reg = <0x0 0x57000000 0x0 0x01000000>, 65 <0x0 0x58000000 0x0 0x01000000>; 82 reg = <0x0 0x17000000 0x0 0x1000000>, 83 <0x0 0x18000000 0x0 0x1000000>; 100 reg = <0x17000000 0x1000000>, 101 <0x18000000 0x1000000>;
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/openbmc/linux/arch/arm/mach-pxa/ |
H A D | addr-map.h | 8 #define PXA_CS0_PHYS 0x00000000 9 #define PXA_CS1_PHYS 0x04000000 10 #define PXA_CS2_PHYS 0x08000000 11 #define PXA_CS3_PHYS 0x0C000000 12 #define PXA_CS4_PHYS 0x10000000 13 #define PXA_CS5_PHYS 0x14000000 15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ 16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ 17 #define PXA3xx_CS2_PHYS 0x10000000 18 #define PXA3xx_CS3_PHYS 0x14000000 [all …]
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H A D | pxa-regs.h | 14 #define UNCACHED_PHYS_0 0xfe000000 15 #define UNCACHED_PHYS_0_SIZE 0x00100000 20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff 21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff 22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff 23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff 24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff 25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff 26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff 31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) [all …]
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/openbmc/u-boot/include/configs/ |
H A D | rcar-gen3-common.h | 28 #define GICD_BASE 0xF1010000 29 #define GICC_BASE 0xF1020000 40 #define DRAM_RSV_SIZE 0x08000000 41 #define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) 42 #define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) 43 #define CONFIG_SYS_LOAD_ADDR 0x58000000 46 #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) 48 #define CONFIG_SYS_MONITOR_BASE 0x00000000 60 "bootm_size=0x10000000\0" 63 "tftp 0x48080000 Image; " \ [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | dra72x.dtsi | 23 reg = <0x58000000 0x80>, 24 <0x58004054 0x4>, 25 <0x58004300 0x20>;
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H A D | dra74x.dtsi | 34 reg = <0x41500000 0x100>; 40 reg = <0x48940000 0x10000>; 49 reg = <0x48950000 0x17000>; 63 reg = <0x41501000 0x100>; 66 #iommu-cells = <0>; 67 ti,syscon-mmuconfig = <&dsp2_system 0x0>; 73 reg = <0x41502000 0x100>; 76 #iommu-cells = <0>; 77 ti,syscon-mmuconfig = <&dsp2_system 0x1>; 88 reg = <0x58000000 0x80>, [all …]
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H A D | tegra186.dtsi | 19 <0x0 0x2200000 0x0 0x10000>, 20 <0x0 0x2210000 0x0 0x10000>; 36 reg = <0x0 0x02490000 0x0 0x10000>; 56 reg = <0x0 0x03100000 0x0 0x10000>; 63 reg = <0x0 0x3160000 0x0 0x100>; 66 #size-cells = <0>; 76 reg = <0x0 0x3180000 0x0 0x100>; 79 #size-cells = <0>; 89 reg = <0x0 0x3190000 0x0 0x100>; 92 #size-cells = <0>; [all …]
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/openbmc/linux/arch/arm/boot/dts/gemini/ |
H A D | gemini.dtsi | 23 pinctrl-0 = <&pflash_default_pins>; 31 reg = <0x40000000 0x1000>; 39 offset = <0x0c>; 41 mask = <0xC0000000>; 49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, 159 reg = <0x41000000 0x1000>; 168 reg = <0x42000000 0x100>; 173 pinctrl-0 = <&uart_default_pins>; 179 reg = <0x43000000 0x1000>; 193 reg = <0x45000000 0x100>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | nvidia,tegra20-mc.yaml | 48 const: 0 69 reg = <0x7000f000 0x400>, /* Controller registers */ 70 <0x58000000 0x02000000>; /* GART aperture */ 74 interrupts = <0 77 4>; 76 #iommu-cells = <0>;
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/openbmc/linux/arch/arm/mach-omap2/ |
H A D | omap24xx.h | 19 #define L4_24XX_BASE 0x48000000 20 #define L4_WK_243X_BASE 0x49000000 21 #define L3_24XX_BASE 0x68000000 24 #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 25 #define OMAP24XX_IVA_INTC_BASE 0x40000000 28 #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 29 #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) 30 #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) 32 #define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) 33 #define OMAP2420_SMS_BASE 0x68008000 [all …]
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H A D | iomap.h | 33 #define OMAP2_L3_IO_OFFSET 0x90000000 36 #define OMAP2_L4_IO_OFFSET 0xb2000000 39 #define OMAP4_L3_IO_OFFSET 0xb4000000 42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000 45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000 48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ 58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ 61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ 65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ 70 /* 0x6e000000 --> 0xfe000000 */ [all …]
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/openbmc/u-boot/board/renesas/sh7785lcr/ |
H A D | lowlevel_init.S | 125 * 0 0xa0000000 0x00000000 1 64M 0 0 126 * 1 0xa4000000 0x04000000 1 16M 0 0 127 * 2 0xa6000000 0x08000000 1 16M 0 0 128 * 9 0x88000000 0x48000000 1 128M 1 1 129 * 10 0x90000000 0x50000000 1 128M 1 1 130 * 11 0x98000000 0x58000000 1 128M 1 1 131 * 13 0xa8000000 0x48000000 1 128M 0 0 132 * 14 0xb0000000 0x50000000 1 128M 0 0 133 * 15 0xb8000000 0x58000000 1 128M 0 0 168 PXCR_D: .word 0x0000 [all …]
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/openbmc/u-boot/board/renesas/sh7752evb/ |
H A D | sh7752evb.c | 19 return 0; in checkboard() 28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio() 29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio() 30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio() 31 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio() 32 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio() 33 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio() 34 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio() 35 writew(0x0003, &gpio->pkcr); /* SerMux */ in init_gpio() 36 writew(0x0000, &gpio->plcr); /* SerMux */ in init_gpio() [all …]
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/openbmc/u-boot/board/renesas/sh7753evb/ |
H A D | sh7753evb.c | 19 return 0; in checkboard() 28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio() 29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio() 30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio() 31 writew(0x0000, &gpio->pdcr); /* SPI0 */ in init_gpio() 32 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio() 33 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio() 34 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ in init_gpio() 35 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio() 36 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio() [all …]
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/openbmc/u-boot/board/renesas/sh7757lcr/ |
H A D | sh7757lcr.c | 19 return 0; in checkboard() 28 writel(graofst | 0x20000f00, &gctrl->gracr3); in init_gctrl() 37 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); in init_pcie_bridge_from_spi() 56 return 0; in init_pcie_bridge_from_spi() 68 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001)) in init_pcie_bridge() 86 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff && in init_pcie_bridge() 87 data[3] == 0xff) { in init_pcie_bridge() 93 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ in init_pcie_bridge() 94 writew(0x0000, &pciebrg->cp_ctrl); in init_pcie_bridge() 95 writew(0x0000, &pciebrg->cp_addr); in init_pcie_bridge() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/ti/ |
H A D | ti,omap-dss.txt | 50 reg = <0x58000000 0x80>; 61 reg = <0x58001000 0x1000>; 70 reg = <0x58006000 0x200>, 71 <0x58006200 0x100>, 72 <0x58006300 0x100>, 73 <0x58006400 0x1000>; 99 tfp410: encoder@0 { 101 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* 0, power-down */ 104 pinctrl-0 = <&tfp410_pins>; 108 #size-cells = <0>; [all …]
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/openbmc/linux/drivers/gpu/drm/etnaviv/ |
H A D | cmdstream.xml.h | 7 http://0x04.net/cgit/index.cgi/rules-ng-ng 8 git clone git://0x04.net/rules-ng-ng 42 #define FE_OPCODE_LOAD_STATE 0x00000001 43 #define FE_OPCODE_END 0x00000002 44 #define FE_OPCODE_NOP 0x00000003 45 #define FE_OPCODE_DRAW_2D 0x00000004 46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005 47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006 48 #define FE_OPCODE_WAIT 0x00000007 49 #define FE_OPCODE_LINK 0x00000008 [all …]
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/openbmc/linux/arch/arm64/boot/dts/renesas/ |
H A D | r9a09g011-v2mevk2.dts | 33 #size-cells = <0>; 35 port@0 { 36 reg = <0>; 57 reg = <0x0 0x58000000 0x0 0x28000000>; 62 reg = <0x1 0x80000000 0x0 0x80000000>; 90 gpios = <&pwc 0 GPIO_ACTIVE_HIGH>; 92 states = <3300000 0>, <1800000 1>; 102 phy0: ethernet-phy@0 { 105 reg = <0>; 110 pinctrl-0 = <&emmc_pins>; [all …]
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/openbmc/qemu/include/hw/arm/ |
H A D | fsl-imx6ul.h | 97 FSL_IMX6UL_MMDC_ADDR = 0x80000000, 100 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000, 103 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, 106 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, 109 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, 112 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, 116 FSL_IMX6UL_UART6_ADDR = 0x021FC000, 118 FSL_IMX6UL_I2C4_ADDR = 0x021F8000, 120 FSL_IMX6UL_UART5_ADDR = 0x021F4000, 121 FSL_IMX6UL_UART4_ADDR = 0x021F0000, [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap5.dtsi | 45 #size-cells = <0>; 47 cpu0: cpu@0 { 50 reg = <0x0>; 69 reg = <0x1>; 115 reg = <0 0x40300000 0 0x20000>; /* 128k */ 122 reg = <0 0x48211000 0 0x1000>, 123 <0 0x48212000 0 0x2000>, 124 <0 0x48214000 0 0x2000>, 125 <0 0x48216000 0 0x2000>; 133 reg = <0 0x48281000 0 0x1000>; [all …]
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H A D | omap4.dtsi | 40 #size-cells = <0>; 42 cpu@0 { 46 reg = <0x0>; 57 reg = <0x1>; 67 reg = <0x40304000 0xa000>; /* 40k */ 74 reg = <0x48241000 0x1000>, 75 <0x48240100 0x0100>; 81 reg = <0x48242000 0x1000>; 89 reg = <0x48240600 0x20>; 98 reg = <0x48281000 0x1000>; [all …]
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/ |
H A D | mmio.c | 21 [INT_SOURCE_CSR] = 0xd7010, 22 [INT_MASK_CSR] = 0xd7014, 23 [INT1_SOURCE_CSR] = 0xd7088, 24 [INT1_MASK_CSR] = 0xd708c, 25 [INT_MCU_CMD_SOURCE] = 0xd51f0, 26 [INT_MCU_CMD_EVENT] = 0x3108, 27 [WFDMA0_ADDR] = 0xd4000, 28 [WFDMA0_PCIE1_ADDR] = 0xd8000, 29 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 30 [CBTOP1_PHY_END] = 0x77ffffff, [all …]
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