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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsocionext,uniphier-xdmac.yaml35 2. Transfer request factor number, If no transfer factor, use 0.
56 reg = <0x5fc10000 0x5300>;
57 interrupts = <0 188 4>;
/openbmc/linux/include/linux/
H A Dapm_bios.h17 #define APM_16_BIT_SUPPORT 0x0001
18 #define APM_32_BIT_SUPPORT 0x0002
19 #define APM_IDLE_SLOWS_CLOCK 0x0004
20 #define APM_BIOS_DISABLED 0x0008
21 #define APM_BIOS_DISENGAGED 0x0010
40 #define APM_FUNC_INST_CHECK 0x5300
41 #define APM_FUNC_REAL_CONN 0x5301
42 #define APM_FUNC_16BIT_CONN 0x5302
43 #define APM_FUNC_32BIT_CONN 0x5303
44 #define APM_FUNC_DISCONN 0x5304
[all …]
/openbmc/u-boot/include/linux/
H A Dapm_bios.h34 #define APM_16_BIT_SUPPORT 0x0001
35 #define APM_32_BIT_SUPPORT 0x0002
36 #define APM_IDLE_SLOWS_CLOCK 0x0004
37 #define APM_BIOS_DISABLED 0x0008
38 #define APM_BIOS_DISENGAGED 0x0010
57 #define APM_FUNC_INST_CHECK 0x5300
58 #define APM_FUNC_REAL_CONN 0x5301
59 #define APM_FUNC_16BIT_CONN 0x5302
60 #define APM_FUNC_32BIT_CONN 0x5303
61 #define APM_FUNC_DISCONN 0x5304
[all …]
/openbmc/linux/include/scsi/
H A Dscsi.h26 #define SCSI_MAX_PROT_SG_SEGMENTS 0xFFFF
32 #define SCAN_WILD_CARD ~0
56 #define SCSI_W_LUN_BASE 0xc100
63 return (lun & 0xff00) == SCSI_W_LUN_BASE; in scsi_is_wlun()
76 if (status < 0) in scsi_status_is_check_condition()
78 status &= 0xfe; in scsi_status_is_check_condition()
85 #define EXTENDED_MODIFY_DATA_POINTER 0x00
86 #define EXTENDED_SDTR 0x01
87 #define EXTENDED_EXTENDED_IDENTIFY 0x02 /* SCSI-I only */
88 #define EXTENDED_WDTR 0x03
[all …]
/openbmc/linux/drivers/usb/host/
H A Dssb-hcd.c45 if (dev->id.revision == 2 && dev->bus->chip_id == 0x5354) { in ssb_hcd_5354wa()
47 ssb_write32(dev, 0x894, 0x00fe00fe); in ssb_hcd_5354wa()
50 ssb_write32(dev, 0x89c, ssb_read32(dev, 0x89c) | 0x1); in ssb_hcd_5354wa()
65 ssb_write32(dev, 0x200, 0x7ff); in ssb_hcd_usb20wa()
68 ssb_write32(dev, 0x400, ssb_read32(dev, 0x400) & ~8); in ssb_hcd_usb20wa()
69 ssb_read32(dev, 0x400); in ssb_hcd_usb20wa()
72 ssb_write32(dev, 0x304, ssb_read32(dev, 0x304) & ~0x100); in ssb_hcd_usb20wa()
73 ssb_read32(dev, 0x304); in ssb_hcd_usb20wa()
84 u32 flags = 0; in ssb_hcd_init_chip()
109 memset(hci_res, 0, sizeof(hci_res)); in ssb_hcd_create_pdev()
[all …]
/openbmc/linux/drivers/net/ethernet/wiznet/
H A Dw5300.c40 #define W5300_MR 0x0000 /* Mode Register */
49 #define MR_IND (1 << 0) /* Indirect mode */
50 #define W5300_IR 0x0002 /* Interrupt Register */
51 #define W5300_IMR 0x0004 /* Interrupt Mask Register */
52 #define IR_S0 0x0001 /* S0 interrupt */
53 #define W5300_SHARL 0x0008 /* Source MAC address (0123) */
54 #define W5300_SHARH 0x000c /* Source MAC address (45) */
55 #define W5300_TMSRL 0x0020 /* Transmit Memory Size (0123) */
56 #define W5300_TMSRH 0x0024 /* Transmit Memory Size (4567) */
57 #define W5300_RMSRL 0x0028 /* Receive Memory Size (0123) */
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Drtl8723b_hal.h27 #define FW_8723B_SIZE 0x8000
28 #define FW_8723B_START_ADDRESS 0x1000
29 #define FW_8723B_END_ADDRESS 0x1FFF /* 0x5FFF */
32 ((le16_to_cpu(fw_hdr->signature) & 0xFFF0) == 0x5300)
43 /* LONG WORD 0 ---- */
53 __le16 subversion; /* FW Subversion, default 0x00 */
73 #define DRIVER_EARLY_INT_TIME_8723B 0x05
74 #define BCN_DMA_ATIME_INT_TIME_8723B 0x02
81 #define RX_DMA_SIZE_8723B 0x4000 /* 16K */
82 #define RX_DMA_RESERVED_SIZE_8723B 0x80 /* 128B, reserved for tx report */
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dov13858.c17 #define OV13858_REG_MODE_SELECT 0x0100
18 #define OV13858_MODE_STANDBY 0x00
19 #define OV13858_MODE_STREAMING 0x01
21 #define OV13858_REG_SOFTWARE_RST 0x0103
22 #define OV13858_SOFTWARE_RST 0x01
25 #define OV13858_REG_PLL1_CTRL_0 0x0300
26 #define OV13858_REG_PLL1_CTRL_1 0x0301
27 #define OV13858_REG_PLL1_CTRL_2 0x0302
28 #define OV13858_REG_PLL1_CTRL_3 0x0303
29 #define OV13858_REG_PLL1_CTRL_4 0x0304
[all …]
H A Dog01a1b.c24 #define OG01A1B_REG_CHIP_ID 0x300a
25 #define OG01A1B_CHIP_ID 0x470141
27 #define OG01A1B_REG_MODE_SELECT 0x0100
28 #define OG01A1B_MODE_STANDBY 0x00
29 #define OG01A1B_MODE_STREAMING 0x01
32 #define OG01A1B_REG_VTS 0x380e
33 #define OG01A1B_VTS_120FPS 0x0498
34 #define OG01A1B_VTS_120FPS_MIN 0x0498
35 #define OG01A1B_VTS_MAX 0x7fff
38 #define OG01A1B_REG_HTS 0x380c
[all …]
/openbmc/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma.h62 #define BCMA_MANUF_ARM 0x43B
63 #define BCMA_MANUF_MIPS 0x4A7
64 #define BCMA_MANUF_BCM 0x4BF
67 #define BCMA_CL_SIM 0x0
68 #define BCMA_CL_EROM 0x1
69 #define BCMA_CL_CORESIGHT 0x9
70 #define BCMA_CL_VERIF 0xB
71 #define BCMA_CL_OPTIMO 0xD
72 #define BCMA_CL_GEN 0xE
73 #define BCMA_CL_PRIMECELL 0xF
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dsw.c30 rtlpci->const_amdpci_aspm = 0; in rtl8723be_init_aspm_vars()
33 * 0 - Disable ASPM, in rtl8723be_init_aspm_vars()
43 rtlpci->const_devicepci_aspm_setting = 0x03; in rtl8723be_init_aspm_vars()
46 rtlpci->const_hostpci_aspm_setting = 0x02; in rtl8723be_init_aspm_vars()
49 * 0 - Default, in rtl8723be_init_aspm_vars()
53 * set default to RTL8192CE:0 RTL8192SE:2 in rtl8723be_init_aspm_vars()
55 rtlpci->const_hwsw_rfoff_d3 = 0; in rtl8723be_init_aspm_vars()
59 * 0 - Not support ASPM, in rtl8723be_init_aspm_vars()
68 int err = 0; in rtl8723be_init_sw_vars()
78 rtlpriv->dm.dm_flag = 0; in rtl8723be_init_sw_vars()
[all …]
/openbmc/libpldm/tests/
H A Dmsgbuf.cpp22 0); in TEST()
31 EXPECT_NE(pldm_msgbuf_init_errno(ctx, sizeof(buf), buf, SIZE_MAX), 0); in TEST()
41 EXPECT_NE(pldm_msgbuf_init_errno(ctx, 0, buf, 2), 0); in TEST()
50 EXPECT_EQ(pldm_msgbuf_init_errno(ctx, sizeof(buf), buf, sizeof(buf)), 0); in TEST()
59 ASSERT_EQ(pldm_msgbuf_init_errno(ctx, sizeof(buf), buf, sizeof(buf)), 0); in TEST()
60 EXPECT_EQ(pldm_msgbuf_destroy(ctx), 0); in TEST()
67 uint8_t buf[1] = {0xa5}; in TEST()
70 ASSERT_EQ(pldm_msgbuf_init_errno(ctx, sizeof(buf), buf, sizeof(buf)), 0); in TEST()
71 EXPECT_EQ(pldm_msgbuf_extract_uint8(ctx, val), 0); in TEST()
72 EXPECT_EQ(val, 0xa5); in TEST()
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7629.c12 MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
15 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
19 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
23 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
27 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
31 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
32 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
33 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
34 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
35 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
[all …]
/openbmc/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi20 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0 0x000>;
46 reg = <0 0x001>;
100 #clock-cells = <0>;
124 reg = <0x0 0x81000000 0x0 0x01000000>;
129 soc@0 {
133 ranges = <0 0 0 0xffffffff>;
138 reg = <0x54006000 0x100>;
140 #size-cells = <0>;
[all …]
H A Duniphier-pxs3.dtsi21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
54 reg = <0 0x001>;
65 reg = <0 0x002>;
76 reg = <0 0x003>;
135 #clock-cells = <0>;
190 reg = <0x0 0x81000000 0x0 0x01000000>;
195 soc@0 {
199 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-ld20.dtsi21 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0 0x000>;
57 reg = <0 0x001>;
68 reg = <0 0x100>;
79 reg = <0 0x101>;
96 cluster0_opp: opp-table-0 {
180 #clock-cells = <0>;
235 reg = <0x0 0x81000000 0x0 0x01000000>;
240 soc@0 {
[all …]
/openbmc/linux/drivers/bcma/
H A Ddriver_pci_host.c34 chipid_top = (bus->chipinfo.id & 0xFF00); in bcma_core_pci_is_in_hostmode()
35 if (chipid_top != 0x4700 && in bcma_core_pci_is_in_hostmode()
36 chipid_top != 0x5300) in bcma_core_pci_is_in_hostmode()
39 bcma_core_enable(pc->core, 0); in bcma_core_pci_is_in_hostmode()
62 u32 addr = 0; in bcma_get_cfgspace_addr()
71 /* Type 0 transaction */ in bcma_get_cfgspace_addr()
90 void __iomem *mmio = 0; in bcma_extpci_read_config()
95 if (dev == 0) { in bcma_extpci_read_config()
96 /* we support only two functions on device 0 */ in bcma_extpci_read_config()
105 addr |= (off & 0x0FFC); in bcma_extpci_read_config()
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro5.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
123 #clock-cells = <0>;
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
139 <0x506c0000 0x400>;
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
166 reg = <0x54006000 0x100>;
[all …]
H A Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]
/openbmc/linux/drivers/ssb/
H A Ddriver_pcicore.c75 u32 addr = 0; in get_cfgspace_addr()
82 if (bus == 0) { in get_cfgspace_addr()
83 /* Type 0 transaction */ in get_cfgspace_addr()
131 val = 0xffffffff; in ssb_extpci_read_config()
149 err = 0; in ssb_extpci_read_config()
162 u32 addr, val = 0; in ssb_extpci_write_config()
177 val = 0xffffffff; in ssb_extpci_write_config()
184 val &= ~(0xFF << (8 * (off & 3))); in ssb_extpci_write_config()
189 val &= ~(0xFFFF << (8 * (off & 3))); in ssb_extpci_write_config()
198 err = 0; in ssb_extpci_write_config()
[all …]
/openbmc/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32f746-pinfunc.h4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13 #define STM32F746_PA0_FUNC_ANALOG 0x11
[all …]
H A Dstm32h7-pinfunc.h4 #define STM32H7_PA0_FUNC_GPIO 0x0
5 #define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32H7_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32H7_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32H7_PA0_FUNC_TIM15_BKIN 0x5
9 #define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8
10 #define STM32H7_PA0_FUNC_UART4_TX 0x9
11 #define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa
12 #define STM32H7_PA0_FUNC_SAI2_SD_B 0xb
13 #define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc
[all …]

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