xref: /openbmc/linux/Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1b9fb56b6SKunihiko Hayashi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2b9fb56b6SKunihiko Hayashi%YAML 1.2
3b9fb56b6SKunihiko Hayashi---
4b9fb56b6SKunihiko Hayashi$id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
5b9fb56b6SKunihiko Hayashi$schema: http://devicetree.org/meta-schemas/core.yaml#
6b9fb56b6SKunihiko Hayashi
7b9fb56b6SKunihiko Hayashititle: Socionext UniPhier external DMA controller
8b9fb56b6SKunihiko Hayashi
9b9fb56b6SKunihiko Hayashidescription: |
10b9fb56b6SKunihiko Hayashi  This describes the devicetree bindings for an external DMA engine to perform
11b9fb56b6SKunihiko Hayashi  memory-to-memory or peripheral-to-memory data transfer capable of supporting
12b9fb56b6SKunihiko Hayashi  16 channels, implemented in Socionext UniPhier SoCs.
13b9fb56b6SKunihiko Hayashi
14b9fb56b6SKunihiko Hayashimaintainers:
15b9fb56b6SKunihiko Hayashi  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
16b9fb56b6SKunihiko Hayashi
17b9fb56b6SKunihiko HayashiallOf:
18*10cafa2dSKrzysztof Kozlowski  - $ref: dma-controller.yaml#
19b9fb56b6SKunihiko Hayashi
20b9fb56b6SKunihiko Hayashiproperties:
21b9fb56b6SKunihiko Hayashi  compatible:
22b9fb56b6SKunihiko Hayashi    const: socionext,uniphier-xdmac
23b9fb56b6SKunihiko Hayashi
24b9fb56b6SKunihiko Hayashi  reg:
25aee45dbaSMasahiro Yamada    maxItems: 1
26b9fb56b6SKunihiko Hayashi
27b9fb56b6SKunihiko Hayashi  interrupts:
28b9fb56b6SKunihiko Hayashi    maxItems: 1
29b9fb56b6SKunihiko Hayashi
30b9fb56b6SKunihiko Hayashi  "#dma-cells":
31b9fb56b6SKunihiko Hayashi    const: 2
32b9fb56b6SKunihiko Hayashi    description: |
33b9fb56b6SKunihiko Hayashi      DMA request from clients consists of 2 cells:
34b9fb56b6SKunihiko Hayashi        1. Channel index
35b9fb56b6SKunihiko Hayashi        2. Transfer request factor number, If no transfer factor, use 0.
36b9fb56b6SKunihiko Hayashi           The number is SoC-specific, and this should be specified with
37b9fb56b6SKunihiko Hayashi           relation to the device to use the DMA controller.
38b9fb56b6SKunihiko Hayashi
39b9fb56b6SKunihiko Hayashi  dma-channels:
40b9fb56b6SKunihiko Hayashi    minimum: 1
41b9fb56b6SKunihiko Hayashi    maximum: 16
42b9fb56b6SKunihiko Hayashi
43b9fb56b6SKunihiko HayashiadditionalProperties: false
44b9fb56b6SKunihiko Hayashi
45b9fb56b6SKunihiko Hayashirequired:
46b9fb56b6SKunihiko Hayashi  - compatible
47b9fb56b6SKunihiko Hayashi  - reg
48b9fb56b6SKunihiko Hayashi  - interrupts
49b9fb56b6SKunihiko Hayashi  - "#dma-cells"
50aee45dbaSMasahiro Yamada  - dma-channels
51b9fb56b6SKunihiko Hayashi
52b9fb56b6SKunihiko Hayashiexamples:
53b9fb56b6SKunihiko Hayashi  - |
54b9fb56b6SKunihiko Hayashi    xdmac: dma-controller@5fc10000 {
55b9fb56b6SKunihiko Hayashi        compatible = "socionext,uniphier-xdmac";
56aee45dbaSMasahiro Yamada        reg = <0x5fc10000 0x5300>;
57b9fb56b6SKunihiko Hayashi        interrupts = <0 188 4>;
58b9fb56b6SKunihiko Hayashi        #dma-cells = <2>;
59b9fb56b6SKunihiko Hayashi        dma-channels = <16>;
60b9fb56b6SKunihiko Hayashi    };
61b9fb56b6SKunihiko Hayashi
62b9fb56b6SKunihiko Hayashi...
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