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/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp131.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
43 #size-cells = <0>;
44 linaro,optee-channel-id = <0>;
47 reg = <0x14>;
52 reg = <0x16>;
57 reg = <0x17>;
61 #size-cells = <0>;
63 scmi_reg11: regulator@0 {
[all …]
H A Dstm32mp151.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
82 #clock-cells = <0>;
[all …]
H A Dstm32f429.dtsi58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
[all …]
H A Dstm32f746.dtsi53 #clock-cells = <0>;
55 clock-frequency = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
80 #size-cells = <0>;
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
102 #size-cells = <0>;
104 reg = <0x40000400 0x400>;
[all …]
H A Dstm32h743.dtsi54 #clock-cells = <0>;
56 clock-frequency = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
68 clock-frequency = <0>;
75 reg = <0x40000c00 0x400>;
82 #size-cells = <0>;
84 reg = <0x40002400 0x400>;
95 trigger@0 {
97 reg = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/openbmc/qemu/hw/arm/
H A Dstm32f100_soc.c39 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
40 0x40004800 };
41 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
53 for (i = 0; i < STM_NUM_USARTS; i++) { in stm32f100_soc_initfn()
58 for (i = 0; i < STM_NUM_SPIS; i++) { in stm32f100_soc_initfn()
62 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); in stm32f100_soc_initfn()
63 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); in stm32f100_soc_initfn()
101 * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 in stm32f100_soc_realize()
106 "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE); in stm32f100_soc_realize()
108 memory_region_add_subregion(system_memory, 0, &s->flash_alias); in stm32f100_soc_realize()
[all …]
H A Dstm32f405_soc.c33 #define RCC_ADDR 0x40023800
34 #define SYSCFG_ADD 0x40013800
35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
36 0x40004C00, 0x40005000, 0x40011400,
37 0x40007800, 0x40007C00 };
39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
40 0x40000800, 0x40000C00 };
41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
42 0x40012300, 0x40012400, 0x40012500 };
43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
[all …]
H A Dstm32l4x5_soc.c36 #define FLASH_BASE_ADDRESS 0x08000000
37 #define SRAM1_BASE_ADDRESS 0x20000000
39 #define SRAM2_BASE_ADDRESS 0x10000000
42 #define EXTI_ADDR 0x40010400
43 #define SYSCFG_ADDR 0x40010000
53 6, /* GPIO[0] */
81 #define RCC_BASE_ADDRESS 0x40021000
114 { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
115 { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
116 { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
[all …]
/openbmc/linux/drivers/pmdomain/renesas/
H A Dr8a77980-sysc.c17 { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON,
20 { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU,
22 { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU,
24 { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU,
26 { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU,
28 { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON,
30 { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON },
31 { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR },
32 { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR },
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2hk-clocks.dtsi13 #clock-cells = <0>;
17 reg = <0x02620370 4>;
22 #clock-cells = <0>;
25 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
30 #clock-cells = <0>;
34 reg = <0x02620358 4>;
39 #clock-cells = <0>;
43 reg = <0x02620360 4>;
48 #clock-cells = <0>;
52 reg = <0x02620368 4>;
[all …]
H A Dstm32f429.dtsi52 #clock-cells = <0>;
54 clock-frequency = <0>;
58 #clock-cells = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
72 clock-frequency = <0>;
79 reg = <0x40000000 0x400>;
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
87 #size-cells = <0>;
89 reg = <0x40000000 0x400>;
[all …]
H A Dkeystone-k2l-clocks.dtsi13 #clock-cells = <0>;
17 reg = <0x02620370 4>;
22 #clock-cells = <0>;
25 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
30 #clock-cells = <0>;
34 reg = <0x02620358 4>;
39 #clock-cells = <0>;
43 reg = <0x02620360 4>;
48 #clock-cells = <0>;
53 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
H A Dstm32mp157c.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
64 reg = <0xa0021000 0x1000>,
65 <0xa0022000 0x2000>;
79 #clock-cells = <0>;
85 #clock-cells = <0>;
91 #clock-cells = <0>;
[all …]
H A Dkeystone-clocks.dtsi17 #clock-cells = <0>;
20 reg = <0x02310108 4>;
27 #clock-cells = <0>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
48 reg = <0x02310120 4>;
49 bit-shift = <0>;
55 #clock-cells = <0>;
58 reg = <0x02310164 4>;
59 bit-shift = <0>;
[all …]
H A Dstm32f746.dtsi56 #clock-cells = <0>;
58 clock-frequency = <0>;
66 reg = <0x40028000 0x8000>;
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
81 reg = <0xA0000000 0x1000>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
89 #size-cells = <0>;
90 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
49 reg = <0x02620368 4>;
[all …]
H A Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
50 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
H A Dkeystone-clocks.dtsi14 #clock-cells = <0>;
17 reg = <0x02310108 4>;
24 #clock-cells = <0>;
33 #clock-cells = <0>;
42 #clock-cells = <0>;
45 reg = <0x02310120 4>;
46 bit-shift = <0>;
52 #clock-cells = <0>;
55 reg = <0x02310164 4>;
56 bit-shift = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Dibm-power11-quad.dtsi126 #size-cells = <0>;
129 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
131 cfam@0,0 {
132 reg = <0 0>;
135 chip-id = <0>;
139 reg = <0x1000 0x400>;
144 reg = <0x1800 0x400>;
146 #size-cells = <0>;
148 cfam0_i2c0: i2c-bus@0 {
149 reg = <0>; /* OMI01 */
[all …]
H A Dibm-power10-quad.dtsi9 reg = <0x20>;
11 #size-cells = <0>;
13 cfam@0,0 {
14 reg = <0 0>;
17 chip-id = <0>;
21 reg = <0x1000 0x400>;
26 reg = <0x2400 0x400>;
28 #size-cells = <0>;
37 reg = <0x20>;
39 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap2.dtsi29 #address-cells = <0>;
30 #size-cells = <0>;
61 reg = <0x480a6000 0x50>;
69 reg = <0x480b2000 0x1000>;
77 reg = <0x480FE000 0x1000>;
82 reg = <0x48056000 0x4>,
83 <0x4805602c 0x4>,
84 <0x48056028 0x4>;
98 ranges = <0 0x48056000 0x1000>;
100 sdma: dma-controller@0 {
[all …]
/openbmc/linux/arch/arm64/boot/dts/st/
H A Dstm32mp251.dtsi14 #size-cells = <0>;
16 cpu0: cpu@0 {
19 reg = <0>;
33 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
60 #size-cells = <0>;
61 linaro,optee-channel-id = <0>;
64 reg = <0x14>;
69 reg = <0x16>;
[all …]
/openbmc/linux/sound/soc/uniphier/
H A Daio-reg.h14 #define SG_AOUTEN 0x1c04
17 #define A2CHNMAPCTR0(n) (0x00000 + 0x40 * (n))
18 #define A2RBNMAPCTR0(n) (0x01000 + 0x40 * (n))
19 #define A2IPORTNMAPCTR0(n) (0x02000 + 0x40 * (n))
20 #define A2IPORTNMAPCTR1(n) (0x02004 + 0x40 * (n))
21 #define A2IIFNMAPCTR0(n) (0x03000 + 0x40 * (n))
22 #define A2OPORTNMAPCTR0(n) (0x04000 + 0x40 * (n))
23 #define A2OPORTNMAPCTR1(n) (0x04004 + 0x40 * (n))
24 #define A2OPORTNMAPCTR2(n) (0x04008 + 0x40 * (n))
25 #define A2OIFNMAPCTR0(n) (0x05000 + 0x40 * (n))
[all …]
/openbmc/linux/drivers/misc/mchp_pci1xxxx/
H A Dmchp_pci1xxxx_gpio.c16 #define PERI_GEN_RESET 0
17 #define OUT_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400)
18 #define INP_EN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x10)
19 #define OUT_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x20)
20 #define INP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x30)
21 #define PULLUP_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x40)
22 #define PULLDOWN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x50)
23 #define OPENDRAIN_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x60)
24 #define WAKEMASK_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x70)
25 #define MODE_OFFSET(x) ((((x) / 32) * 4) + 0x400 + 0x80)
[all …]

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