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/openbmc/qemu/include/hw/s390x/
H A Debcdic.h17 0x00, 0x01, 0x02, 0x03, 0x07, 0x09, 0x07, 0x7F,
18 0x07, 0x07, 0x07, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
19 0x10, 0x11, 0x12, 0x13, 0x07, 0x0A, 0x08, 0x07,
20 0x18, 0x19, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
21 0x07, 0x07, 0x1C, 0x07, 0x07, 0x0A, 0x17, 0x1B,
22 0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x06, 0x07,
23 0x07, 0x07, 0x16, 0x07, 0x07, 0x07, 0x07, 0x04,
24 0x07, 0x07, 0x07, 0x07, 0x14, 0x15, 0x07, 0x1A,
25 0x20, 0xFF, 0x83, 0x84, 0x85, 0xA0, 0x07, 0x86,
26 0x87, 0xA4, 0x5B, 0x2E, 0x3C, 0x28, 0x2B, 0x21,
[all …]
/openbmc/linux/arch/s390/kernel/
H A Debcdic.c22 0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F,
25 0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
27 0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26,
30 0x18, 0x19, 0x3F, 0x27, 0x22, 0x1D, 0x1E, 0x1F,
32 0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D,
34 0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61,
35 /*30 0 1 2 3 4 5 6 7 */
36 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
38 0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F,
40 0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
[all …]
/openbmc/u-boot/include/
H A Dvideo_logo.h22 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
23 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
24 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
25 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6,
26 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xe1,
27 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
28 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
29 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
30 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
31 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
[all …]
/openbmc/qemu/target/ppc/translate/
H A Dfp-ops.c.inc2 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
4 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
5 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
6 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
7 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
8 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
11 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
12 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dinitvals_phy.h12 { MT_RF(0, 1), 0x01 },
13 { MT_RF(0, 2), 0x11 },
15 { MT_RF(0, 3), 0x73 }, /* VCO Freq Cal */
16 { MT_RF(0, 4), 0x30 }, /* R4 b<7>=1, VCO cal */
17 { MT_RF(0, 5), 0x00 },
18 { MT_RF(0, 6), 0x41 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
22 { MT_RF(0, 10), 0x0C },
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_s10.h16 #define DDR_ACTIVATE_FAWBANK 0x1
19 #define DDRIOCTRL 0x8
20 #define DDRCALSTAT 0xc
21 #define DRAMADDRWIDTH 0xe0
22 #define ECCCTRL1 0x100
23 #define ECCCTRL2 0x104
24 #define ERRINTEN 0x110
25 #define INTMODE 0x11c
26 #define INTSTAT 0x120
27 #define AUTOWB_CORRADDR 0x138
[all …]
/openbmc/u-boot/drivers/power/regulator/
H A Ds5m8767.c50 {S5M8767_BUCK1, 0x33, 0x0, 0xff, 0x32, 0x3, &buck_v1},
51 {S5M8767_BUCK2, 0x35, 0x0, 0xff, 0x34, 0x1, &buck_v2},
52 {S5M8767_BUCK3, 0x3e, 0x0, 0xff, 0x3d, 0x1, &buck_v2},
53 {S5M8767_BUCK4, 0x47, 0x0, 0xff, 0x46, 0x1, &buck_v2},
54 {S5M8767_BUCK5, 0x50, 0x0, 0xff, 0x4f, 0x3, &buck_v1},
55 {S5M8767_BUCK6, 0x55, 0x0, 0xff, 0x54, 0x3, &buck_v1},
56 {S5M8767_BUCK7, 0x57, 0x0, 0xff, 0x56, 0x3, &buck_v3},
57 {S5M8767_BUCK8, 0x59, 0x0, 0xff, 0x58, 0x3, &buck_v3},
58 {S5M8767_BUCK9, 0x5b, 0x0, 0xff, 0x5a, 0x3, &buck_v3},
62 {S5M8767_LDO1, 0x5c, 0x0, 0x3f, 0x5c, 0x3, &ldo_v2},
[all …]
/openbmc/linux/drivers/gpu/drm/panel/
H A Dpanel-raydium-rm68200.c22 #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
23 #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
24 #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
25 #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
26 #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
27 #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
30 #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
31 #define MCS_SGOPCTR 0x16 /* Source Bias Current */
32 #define MCS_SDCTR 0x1A /* Source Output Delay Time */
33 #define MCS_INVCTR 0x1B /* Inversion Type */
[all …]
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_s6d1121.c24 #define DEFAULT_GAMMA "26 09 24 2C 1F 23 24 25 22 26 25 23 0D 00\n" \
25 "1C 1A 13 1D 0B 11 12 10 13 15 36 19 00 0D"
33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
40 write_reg(par, 0x0013, 0xCC4F); in init_display()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs42l73.c47 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
48 { 7, 0xDF }, /* r07 - Power Ctl 2 */
49 { 8, 0x3F }, /* r08 - Power Ctl 3 */
50 { 9, 0x50 }, /* r09 - Charge Pump Freq */
51 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
52 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
53 { 12, 0x00 }, /* r0C - Aux PCM Ctl */
54 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
55 { 14, 0x00 }, /* r0E - Audio PCM Ctl */
56 { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */
[all …]
/openbmc/linux/drivers/video/fbdev/via/
H A Dhw.c13 {19, 19, 4, 0},
14 {26, 102, 5, 0},
15 {53, 112, 6, 0},
16 {41, 100, 7, 0},
17 {83, 108, 8, 0},
18 {87, 118, 9, 0},
19 {95, 115, 12, 0},
20 {108, 108, 13, 0},
21 {83, 83, 17, 0},
22 {67, 98, 20, 0},
[all …]
/openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/
H A Djz4780_dram.h15 #define DDRC_ST 0x0
16 #define DDRC_CFG 0x4
17 #define DDRC_CTRL 0x8
18 #define DDRC_LMR 0xc
19 #define DDRC_REFCNT 0x18
20 #define DDRC_DQS 0x1c
21 #define DDRC_DQS_ADJ 0x20
22 #define DDRC_MMAP0 0x24
23 #define DDRC_MMAP1 0x28
24 #define DDRC_MDELAY 0x2c
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ecc.c41 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
42 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
43 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
44 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
45 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
46 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
47 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
48 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
49 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
50 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d3_smc.h13 #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600)
14 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604)
15 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608)
16 #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c)
17 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610)
20 u32 setup; /* 0x600 SMC Setup Register */
21 u32 pulse; /* 0x604 SMC Pulse Register */
22 u32 cycle; /* 0x608 SMC Cycle Register */
23 u32 timings; /* 0x60C SMC Cycle Register */
24 u32 mode; /* 0x610 SMC Mode Register */
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmme1_rtr_masks.h23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0
24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7
26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700
28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000
30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000
33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0
34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7
36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700
38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000
40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx35/
H A Dcrm_regs.h15 #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
17 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
19 #define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16)
21 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
28 #define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20)
30 #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
33 #define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12)
35 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
36 #define MXC_CCM_PDR0_AUTO_CON 0x1
39 #define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28)
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dhvx_histogram_input.h18 { 0x26, 0x32, 0x2e, 0x2e, 0x2d, 0x2c, 0x2d, 0x2d,
19 0x2c, 0x2e, 0x31, 0x33, 0x36, 0x39, 0x3b, 0x3f,
20 0x42, 0x46, 0x4a, 0x4c, 0x51, 0x53, 0x53, 0x54,
21 0x56, 0x57, 0x58, 0x57, 0x56, 0x52, 0x51, 0x4f,
22 0x4c, 0x49, 0x47, 0x42, 0x3e, 0x3b, 0x38, 0x35,
23 0x33, 0x30, 0x2e, 0x2c, 0x2b, 0x2a, 0x2a, 0x28,
24 0x28, 0x27, 0x27, 0x28, 0x29, 0x2a, 0x2c, 0x2e,
25 0x2f, 0x33, 0x36, 0x38, 0x3c, 0x3d, 0x40, 0x42,
26 0x43, 0x42, 0x43, 0x44, 0x43, 0x41, 0x40, 0x3b,
27 0x3b, 0x3a, 0x38, 0x35, 0x32, 0x2f, 0x2c, 0x29,
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dnid.h33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
39 #define CAYMAN_MAX_PIPES_MASK 0xFF
40 #define CAYMAN_MAX_LDS_NUM 0xFFFF
42 #define CAYMAN_MAX_TCC_MASK 0xFF
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
47 #define DMIF_ADDR_CONFIG 0xBD4
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2059.c17 { 0x051, 0x70 }, { 0x05a, 0x03 }, { 0x079, 0x01 }, { 0x082, 0x70 },
18 { 0x083, 0x00 }, { 0x084, 0x70 }, { 0x09a, 0x7f }, { 0x0b6, 0x10 },
19 { 0x188, 0x05 },
61 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
62 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
63 0x00, 0x00, 0x00, 0xd0, 0x00),
64 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
68 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
69 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
70 0x00, 0x00, 0x00, 0xd0, 0x00),
[all …]
/openbmc/u-boot/lib/
H A Dcharset.c31 s32 ch = 0; in get_code()
35 return 0; in get_code()
36 if (ch >= 0xc2 && ch <= 0xf4) { in get_code()
37 int code = 0; in get_code()
39 if (ch >= 0xe0) { in get_code()
40 if (ch >= 0xf0) { in get_code()
41 /* 0xf0 - 0xf4 */ in get_code()
42 ch &= 0x07; in get_code()
45 if (ch < 0x80 || ch > 0xbf) in get_code()
47 ch &= 0x3f; in get_code()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c19 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
20 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
21 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
22 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
23 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
24 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
25 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
26 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
27 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
36 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
[all …]
/openbmc/linux/drivers/net/wireless/intersil/orinoco/
H A Dhermes_dld.c50 #define PDI_END 0x00000000 /* End of PDA */
51 #define BLOCK_END 0xFFFFFFFF /* Last image block */
52 #define TEXT_END 0x1A /* End of text header */
160 * field where PDR has length. The type can be 0 or 1. in hermes_find_pdr()
206 return 0; in hermes_plug_pdi()
215 return 0; in hermes_plug_pdi()
247 return 0; in hermes_apply_pda()
257 int total_len = 0; in hermes_blocks_length()
282 int err = 0; in hermes_program()
295 "to address 0x%08x\n", blklen, blkaddr); in hermes_program()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h11 #define CAAM_SEC_SRAM_BASE (0x26000000)
15 #define OCRAM_0_BASE (0x2F000000)
19 #define OCRAM_1_BASE (0x2F020000)
23 #define TCML_BASE (0x1FFD0000)
24 #define TCMU_BASE (0x20000000)
26 #define AIPS3_BASE (0x40800000UL)
28 #define AIPS2_BASE (0x40000000UL)
30 #define AIPS1_BASE (0x41080000UL)
32 #define AIPS0_BASE (0x41000000UL)
87 #define CORE_B_ROM_BASE (0x00000000)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dscu_ast2500.h8 #define SCU_UNLOCK_VALUE 0x1688a8a8
18 #define SCU_MPLL_DENUM_SHIFT 0
19 #define SCU_MPLL_DENUM_MASK 0x1f
21 #define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
23 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
26 #define SCU_HPLL_DENUM_SHIFT 0
27 #define SCU_HPLL_DENUM_MASK 0x1f
29 #define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
31 #define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
48 #define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0
[all …]
/openbmc/linux/include/linux/mfd/da9052/
H A Dreg.h14 #define DA9052_PAGE0_CON_REG 0
176 #define DA9052_PAGE_CONF 0X80
179 #define DA9052_STATUSA_VDATDET 0X80
180 #define DA9052_STATUSA_VBUSSEL 0X40
181 #define DA9052_STATUSA_DCINSEL 0X20
182 #define DA9052_STATUSA_VBUSDET 0X10
183 #define DA9052_STATUSA_DCINDET 0X08
184 #define DA9052_STATUSA_IDGND 0X04
185 #define DA9052_STATUSA_IDFLOAT 0X02
186 #define DA9052_STATUSA_NONKEY 0X01
[all …]

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