/openbmc/linux/drivers/clk/hisilicon/ |
H A D | clk-hi6220.c | 23 { HI6220_REF32K, "ref32k", NULL, 0, 32764, }, 24 { HI6220_CLK_TCXO, "clk_tcxo", NULL, 0, 19200000, }, 25 { HI6220_MMC1_PAD, "mmc1_pad", NULL, 0, 100000000, }, 26 { HI6220_MMC2_PAD, "mmc2_pad", NULL, 0, 100000000, }, 27 { HI6220_MMC0_PAD, "mmc0_pad", NULL, 0, 200000000, }, 28 { HI6220_PLL_BBP, "bbppll0", NULL, 0, 245760000, }, 29 { HI6220_PLL_GPU, "gpupll", NULL, 0, 1000000000,}, 30 { HI6220_PLL1_DDR, "ddrpll1", NULL, 0, 1066000000,}, 31 { HI6220_PLL_SYS, "syspll", NULL, 0, 1190400000,}, 32 { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,}, [all …]
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 9 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28 10 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c 11 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 12 #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 14 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 15 #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 16 #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 17 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 18 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c 19 #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214 [all …]
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/openbmc/linux/drivers/gpu/drm/i915/gt/ |
H A D | intel_lrc.c | 32 * [5:0]: Number of NOPs or registers to set values to in case of 37 * is used for offsets smaller than 0x200 while the latter is for values bigger 42 * [6:0]: Register offset, without considering the engine base. 53 #define POSTED BIT(0) in set_offsets() 54 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets() 56 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets() 57 (((x) >> 2) & 0x7f) in set_offsets() 58 #define END 0 in set_offsets() 71 count = *data & 0x3f; in set_offsets() 84 u32 offset = 0; in set_offsets() [all …]
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H A D | intel_engine_regs.h | 11 #define RING_EXCC(base) _MMIO((base) + 0x28) 12 #define RING_TAIL(base) _MMIO((base) + 0x30) 13 #define TAIL_ADDR 0x001FFFF8 14 #define RING_HEAD(base) _MMIO((base) + 0x34) 15 #define HEAD_WRAP_COUNT 0xFFE00000 16 #define HEAD_WRAP_ONE 0x00200000 17 #define HEAD_ADDR 0x001FFFFC 18 #define RING_START(base) _MMIO((base) + 0x38) 19 #define RING_CTL(base) _MMIO((base) + 0x3c) 21 #define RING_NR_PAGES 0x001FF000 [all …]
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt6795-apmixedsys.c | 15 #define REG_REF2USB 0x8 16 #define REG_AP_PLL_CON7 0x1c 17 #define MD1_MTCMOS_OFF BIT(0) 23 #define MT6795_CON0_EN BIT(0) 43 .pll_en_bit = 0, \ 47 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO, 48 21, 0x204, 24, 0x0, 0x204, 0), 49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 50 21, 0x220, 4, 0x0, 0x224, 0), 51 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR, [all …]
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H A D | clk-mt8173-apmixedsys.c | 17 #define REGOFF_REF2USB 0x8 18 #define REGOFF_HDMI_REF 0x40 52 { .div = 0, .freq = MT8173_PLL_FMAX }, 61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO, 62 21, 0x204, 24, 0x0, 0x204, 0), 63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO, 64 21, 0x214, 24, 0x0, 0x214, 0), 65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21, 66 0x220, 4, 0x0, 0x224, 0), 67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7, [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/ |
H A D | mc.h | 14 u32 reserved0[3]; /* offset 0x00 - 0x08 */ 15 u32 mc_emem_cfg; /* offset 0x0C */ 16 u32 mc_emem_adr_cfg; /* offset 0x10 */ 17 u32 mc_emem_arb_cfg0; /* offset 0x14 */ 18 u32 mc_emem_arb_cfg1; /* offset 0x18 */ 19 u32 mc_emem_arb_cfg2; /* offset 0x1C */ 20 u32 reserved1; /* offset 0x20 */ 21 u32 mc_gart_cfg; /* offset 0x24 */ 22 u32 mc_gart_entry_addr; /* offset 0x28 */ 23 u32 mc_gart_entry_data; /* offset 0x2C */ [all …]
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/openbmc/linux/drivers/soc/tegra/fuse/ |
H A D | speedo-tegra114.c | 25 {0, UINT_MAX}, 30 {0, UINT_MAX}, 41 case 0x00: in rev_sku_to_speedo_ids() 42 case 0x10: in rev_sku_to_speedo_ids() 43 case 0x05: in rev_sku_to_speedo_ids() 44 case 0x06: in rev_sku_to_speedo_ids() 46 sku_info->soc_speedo_id = 0; in rev_sku_to_speedo_ids() 50 case 0x03: in rev_sku_to_speedo_ids() 51 case 0x04: in rev_sku_to_speedo_ids() 59 sku_info->cpu_speedo_id = 0; in rev_sku_to_speedo_ids() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/arm/omap/ |
H A D | ctrl.txt | 41 reg = <0x2000 0x2000>; 44 ranges = <0 0x2000 0x2000>; 49 reg = <0x30 0x230>; 51 #size-cells = <0>; 55 pinctrl-single,function-mask = <0xff1f>; 60 reg = <0x270 0x330>; 66 #size-cells = <0>; 76 #clock-cells = <0>; 80 reg = <0x02d8>;
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap2430.dtsi | 18 ranges = <0 0x49000000 0x31000>; 22 reg = <0x6000 0x1000>; 26 #size-cells = <0>; 35 reg = <0x2000 0x1000>; 39 ranges = <0 0x2000 0x1000>; 44 reg = <0x30 0x0154>; 46 #size-cells = <0>; 49 pinctrl-single,function-mask = <0x3f>; 55 reg = <0x270 0x240>; 58 ranges = <0 0x270 0x240>; [all …]
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/openbmc/linux/drivers/pinctrl/ |
H A D | pinctrl-pic32.h | 12 #define ANSEL_REG 0x00 13 #define TRIS_REG 0x10 14 #define PORT_REG 0x20 15 #define LAT_REG 0x30 16 #define ODCU_REG 0x40 17 #define CNPU_REG 0x50 18 #define CNPD_REG 0x60 19 #define CNCON_REG 0x70 20 #define CNEN_REG 0x80 21 #define CNSTAT_REG 0x90 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/ |
H A D | mc.h | 13 u32 reserved0[4]; /* offset 0x00 - 0x0C */ 14 u32 mc_smmu_config; /* offset 0x10 */ 15 u32 mc_smmu_tlb_config; /* offset 0x14 */ 16 u32 mc_smmu_ptc_config; /* offset 0x18 */ 17 u32 mc_smmu_ptb_asid; /* offset 0x1C */ 18 u32 mc_smmu_ptb_data; /* offset 0x20 */ 19 u32 reserved1[3]; /* offset 0x24 - 0x2C */ 20 u32 mc_smmu_tlb_flush; /* offset 0x30 */ 21 u32 mc_smmu_ptc_flush; /* offset 0x34 */ 22 u32 reserved2[6]; /* offset 0x38 - 0x4C */ [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-tegra210/ |
H A D | mc.h | 13 u32 reserved0[4]; /* offset 0x00 - 0x0C */ 14 u32 mc_smmu_config; /* offset 0x10 */ 15 u32 mc_smmu_tlb_config; /* offset 0x14 */ 16 u32 mc_smmu_ptc_config; /* offset 0x18 */ 17 u32 mc_smmu_ptb_asid; /* offset 0x1C */ 18 u32 mc_smmu_ptb_data; /* offset 0x20 */ 19 u32 reserved1[3]; /* offset 0x24 - 0x2C */ 20 u32 mc_smmu_tlb_flush; /* offset 0x30 */ 21 u32 mc_smmu_ptc_flush; /* offset 0x34 */ 22 u32 reserved2[6]; /* offset 0x38 - 0x4C */ [all …]
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/openbmc/linux/arch/arm/include/asm/ |
H A D | v7m.h | 5 #define V7M_SCS_ICTR IOMEM(0xe000e004) 6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f 8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00) 10 #define V7M_SCB_CPUID 0x00 12 #define V7M_SCB_ICSR 0x04 16 #define V7M_SCB_ICSR_VECTACTIVE 0x000001ff 18 #define V7M_SCB_VTOR 0x08 20 #define V7M_SCB_AIRCR 0x0c 21 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16) 24 #define V7M_SCB_SCR 0x10 [all …]
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/openbmc/linux/tools/perf/arch/powerpc/util/ |
H A D | book3s_hcalls.h | 9 {0x4, "H_REMOVE"}, \ 10 {0x8, "H_ENTER"}, \ 11 {0xc, "H_READ"}, \ 12 {0x10, "H_CLEAR_MOD"}, \ 13 {0x14, "H_CLEAR_REF"}, \ 14 {0x18, "H_PROTECT"}, \ 15 {0x1c, "H_GET_TCE"}, \ 16 {0x20, "H_PUT_TCE"}, \ 17 {0x24, "H_SET_SPRG0"}, \ 18 {0x28, "H_SET_DABR"}, \ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/arm/apple/ |
H A D | apple,pmgr.yaml | 20 pattern: "^power-management@[0-9a-f]+$" 42 "power-controller@[0-9a-f]+$": 64 reg = <0x2 0x3b700000 0x0 0x14000>; 68 reg = <0x1c0 8>; 69 #power-domain-cells = <0>; 70 #reset-cells = <0>; 77 reg = <0x220 8>; 78 #power-domain-cells = <0>; 79 #reset-cells = <0>; 86 reg = <0x270 8>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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H A D | imx35-pinfunc.h | 13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 [all …]
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/openbmc/u-boot/board/freescale/mx6ullevk/ |
H A D | plugin.S | 11 ldr r1, =0x000C0000 12 str r1, [r0, #0x4B4] 13 ldr r1, =0x00000000 14 str r1, [r0, #0x4AC] 15 ldr r1, =0x00000030 16 str r1, [r0, #0x27C] 17 ldr r1, =0x00000030 18 str r1, [r0, #0x250] 19 str r1, [r0, #0x24C] 20 str r1, [r0, #0x490] [all …]
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/openbmc/linux/arch/sh/include/mach-sdk7786/mach/ |
H A D | fpga.h | 9 #define SRSTR 0x000 10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */ 12 #define INTASR 0x010 13 #define INTAMR 0x020 14 #define MODSWR 0x030 15 #define INTTESTR 0x040 16 #define SYSSR 0x050 17 #define NRGPR 0x060 19 #define NMISR 0x070 20 #define NMISR_MAN_NMI BIT(0) [all …]
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/openbmc/linux/Documentation/sound/cards/ |
H A D | multisound.sh | 77 # 0x250, 0x260 or 0x270. This port can be disabled to have the card 96 # to obtain one with the command `pnpdump 1 0x203' -- this may vary 107 # io base 0x210, irq 5 and mem 0xd8000, and also sets the Kurzweil 108 # synth to 0x330 and irq 9 (may need editing for your system): 110 # (READPORT 0x0203) 115 # (CONFIGURE BVJ0440/-1 (LD 0 116 # (INT 0 (IRQ 5 (MODE +E))) (IO 0 (BASE 0x0210)) (MEM 0 (BASE 0x0d8000)) 121 # (IO 0 (BASE 0x0330)) (INT 0 (IRQ 9 (MODE +E))) 140 # If you specify cfg=0x250 for the snd-msnd-pinnacle module, it 143 # on the card to 0x250, 0x260 or 0x270). [all …]
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/openbmc/u-boot/drivers/ddr/marvell/axp/ |
H A D | xor_regs.h | 11 * to channels 0 & 1 of unit 1 16 #define MV_XOR_REGS_OFFSET(unit) (0x60900) 21 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4))) 22 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4))) 25 #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x30) 26 #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x40) 27 #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x50) 28 #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x60) 31 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4))) 32 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4))) [all …]
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/openbmc/linux/drivers/media/pci/tw68/ |
H A D | tw68-reg.h | 23 #define TW68_DMAC 0x000 24 #define TW68_DMAP_SA 0x004 25 #define TW68_DMAP_EXE 0x008 26 #define TW68_DMAP_PP 0x00c 27 #define TW68_VBIC 0x010 28 #define TW68_SBUSC 0x014 29 #define TW68_SBUSSD 0x018 30 #define TW68_INTSTAT 0x01C 31 #define TW68_INTMASK 0x020 32 #define TW68_GPIOC 0x024 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mxs/ |
H A D | regs-ocotp.h | 19 mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */ 20 mxs_reg_32(hw_ocotp_data) /* 0x10 */ 21 mxs_reg_32(hw_ocotp_cust0) /* 0x20 */ 22 mxs_reg_32(hw_ocotp_cust1) /* 0x30 */ 23 mxs_reg_32(hw_ocotp_cust2) /* 0x40 */ 24 mxs_reg_32(hw_ocotp_cust3) /* 0x50 */ 25 mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */ 26 mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */ 27 mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */ 28 mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */ [all …]
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