1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 28c33ba7bSMarcel Ziswiler /* 38c33ba7bSMarcel Ziswiler * (C) Copyright 2014 48c33ba7bSMarcel Ziswiler * NVIDIA Corporation <www.nvidia.com> 58c33ba7bSMarcel Ziswiler */ 68c33ba7bSMarcel Ziswiler 78c33ba7bSMarcel Ziswiler #ifndef _TEGRA20_MC_H_ 88c33ba7bSMarcel Ziswiler #define _TEGRA20_MC_H_ 98c33ba7bSMarcel Ziswiler 108c33ba7bSMarcel Ziswiler /** 118c33ba7bSMarcel Ziswiler * Defines the memory controller registers we need/care about 128c33ba7bSMarcel Ziswiler */ 138c33ba7bSMarcel Ziswiler struct mc_ctlr { 148c33ba7bSMarcel Ziswiler u32 reserved0[3]; /* offset 0x00 - 0x08 */ 158c33ba7bSMarcel Ziswiler u32 mc_emem_cfg; /* offset 0x0C */ 168c33ba7bSMarcel Ziswiler u32 mc_emem_adr_cfg; /* offset 0x10 */ 178c33ba7bSMarcel Ziswiler u32 mc_emem_arb_cfg0; /* offset 0x14 */ 188c33ba7bSMarcel Ziswiler u32 mc_emem_arb_cfg1; /* offset 0x18 */ 198c33ba7bSMarcel Ziswiler u32 mc_emem_arb_cfg2; /* offset 0x1C */ 208c33ba7bSMarcel Ziswiler u32 reserved1; /* offset 0x20 */ 218c33ba7bSMarcel Ziswiler u32 mc_gart_cfg; /* offset 0x24 */ 228c33ba7bSMarcel Ziswiler u32 mc_gart_entry_addr; /* offset 0x28 */ 238c33ba7bSMarcel Ziswiler u32 mc_gart_entry_data; /* offset 0x2C */ 248c33ba7bSMarcel Ziswiler u32 mc_gart_error_req; /* offset 0x30 */ 258c33ba7bSMarcel Ziswiler u32 mc_gart_error_addr; /* offset 0x34 */ 268c33ba7bSMarcel Ziswiler u32 reserved2; /* offset 0x38 */ 278c33ba7bSMarcel Ziswiler u32 mc_timeout_ctrl; /* offset 0x3C */ 288c33ba7bSMarcel Ziswiler u32 reserved3[6]; /* offset 0x40 - 0x54 */ 298c33ba7bSMarcel Ziswiler u32 mc_decerr_emem_others_status; /* offset 0x58 */ 308c33ba7bSMarcel Ziswiler u32 mc_decerr_emem_others_adr; /* offset 0x5C */ 318c33ba7bSMarcel Ziswiler u32 reserved4[40]; /* offset 0x60 - 0xFC */ 328c33ba7bSMarcel Ziswiler u32 reserved5[93]; /* offset 0x100 - 0x270 */ 338c33ba7bSMarcel Ziswiler }; 348c33ba7bSMarcel Ziswiler 358c33ba7bSMarcel Ziswiler #endif /* _TEGRA20_MC_H_ */ 36