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/openbmc/linux/drivers/net/wireless/marvell/mwifiex/
H A D11ac.c18 {0x124, 0x15F, 0x186}, /* NSS = 1 */
19 {0x249, 0x2BE, 0x30C}, /* NSS = 2 */
20 {0x36D, 0x41D, 0x492}, /* NSS = 3 */
21 {0x492, 0x57C, 0x618}, /* NSS = 4 */
22 {0x5B6, 0x6DB, 0x79E}, /* NSS = 5 */
23 {0x6DB, 0x83A, 0x0}, /* NSS = 6 */
24 {0x7FF, 0x999, 0xAAA}, /* NSS = 7 */
25 {0x924, 0xAF8, 0xC30} /* NSS = 8 */
29 {0x249, 0x2BE, 0x30C}, /* NSS = 1 */
30 {0x492, 0x57C, 0x618}, /* NSS = 2 */
[all …]
H A Dcfp.c28 static u8 adhoc_rates_b[B_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 0 };
30 static u8 adhoc_rates_g[G_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
31 0xb0, 0x48, 0x60, 0x6c, 0 };
33 static u8 adhoc_rates_bg[BG_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96,
34 0x0c, 0x12, 0x18, 0x24,
35 0x30, 0x48, 0x60, 0x6c, 0 };
37 static u8 adhoc_rates_a[A_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
38 0xb0, 0x48, 0x60, 0x6c, 0 };
39 static u8 supported_rates_a[A_SUPPORTED_RATES] = { 0x0c, 0x12, 0x18, 0x24,
40 0xb0, 0x48, 0x60, 0x6c, 0 };
[all …]
/openbmc/linux/drivers/media/platform/ti/am437x/
H A Dam437x-vpfe_regs.h15 #define VPFE_REVISION 0x0
16 #define VPFE_PCR 0x4
17 #define VPFE_SYNMODE 0x8
18 #define VPFE_HD_VD_WID 0xc
19 #define VPFE_PIX_LINES 0x10
20 #define VPFE_HORZ_INFO 0x14
21 #define VPFE_VERT_START 0x18
22 #define VPFE_VERT_LINES 0x1c
23 #define VPFE_CULLING 0x20
24 #define VPFE_HSIZE_OFF 0x24
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,cci-400.yaml24 pattern: "^cci(@[0-9a-f]+)?$"
43 "^slave-if@[0-9a-f]+$":
65 "^pmu@[0-9a-f]+$":
119 arm,hbi = <0x249>;
129 * registers sits at address 0x000000002c090000.
131 * CCI slave interface @0x000000002c091000 is connected to dma
134 * CCI slave interface @0x000000002c094000 is connected to CPUs
137 * CCI slave interface @0x000000002c095000 is connected to CPUs
142 #size-cells = <0>;
145 CPU0: cpu@0 {
[all …]
/openbmc/linux/drivers/usb/serial/
H A Dsafe_serial.c35 * 0..N-2 data and optional padding
38 * bits 1-0 top two bits of 10 bit CRC
43 * + 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 | 7 . 6 . 5 . 4 . 3 . 2 . 1 . 0 +
85 module_param(safe, bool, 0);
88 module_param(padded, bool, 0);
91 #define CDC_DEVICE_CLASS 0x02
93 #define CDC_INTERFACE_CLASS 0x02
94 #define CDC_INTERFACE_SUBCLASS 0x06
96 #define LINEO_INTERFACE_CLASS 0xff
98 #define LINEO_INTERFACE_SUBCLASS_SAFENET 0x01
[all …]
/openbmc/u-boot/arch/arm/mach-imx/
H A Dcpu.c49 case 0x00001: in get_reset_cause()
50 case 0x00011: in get_reset_cause()
52 case 0x00004: in get_reset_cause()
54 case 0x00008: in get_reset_cause()
56 case 0x00010: in get_reset_cause()
62 case 0x00020: in get_reset_cause()
64 case 0x00040: in get_reset_cause()
66 case 0x00080: in get_reset_cause()
69 case 0x00100: in get_reset_cause()
71 case 0x00200: in get_reset_cause()
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dcontrol.h48 #define OMAP2_CONTROL_INTERFACE 0x000
49 #define OMAP2_CONTROL_PADCONFS 0x030
50 #define OMAP2_CONTROL_GENERAL 0x270
51 #define OMAP343X_CONTROL_MEM_WKUP 0x600
52 #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
53 #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60
56 #define TI81XX_CONTROL_DEVBOOT 0x040
57 #define TI81XX_CONTROL_DEVCONF 0x600
61 #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10)
64 #define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004)
[all …]
/openbmc/linux/sound/drivers/opl4/
H A Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/openbmc/linux/drivers/video/fbdev/sis/
H A Dinitdef.h77 #define VB_SIS301 0x0001
78 #define VB_SIS301B 0x0002
79 #define VB_SIS302B 0x0004
80 #define VB_SIS301LV 0x0008
81 #define VB_SIS302LV 0x0010
82 #define VB_SIS302ELV 0x0020
83 #define VB_SIS301C 0x0040
84 #define VB_SIS307T 0x0080
85 #define VB_SIS307LV 0x0100
86 #define VB_UMC 0x4000
[all …]
/openbmc/linux/drivers/power/supply/
H A Dqcom_smbb.c32 #define SMBB_CHG_VMAX 0x040
33 #define SMBB_CHG_VSAFE 0x041
34 #define SMBB_CHG_CFG 0x043
35 #define SMBB_CHG_IMAX 0x044
36 #define SMBB_CHG_ISAFE 0x045
37 #define SMBB_CHG_VIN_MIN 0x047
38 #define SMBB_CHG_CTRL 0x049
40 #define SMBB_CHG_VBAT_WEAK 0x052
41 #define SMBB_CHG_IBAT_TERM_CHG 0x05b
44 #define IBAT_TERM_CHG_IEOC_CHG 0
[all …]
/openbmc/linux/include/uapi/linux/
H A Dinput-event-codes.h23 #define INPUT_PROP_POINTER 0x00 /* needs a pointer */
24 #define INPUT_PROP_DIRECT 0x01 /* direct input devices */
25 #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
26 #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
27 #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
28 #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
29 #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
31 #define INPUT_PROP_MAX 0x1f
38 #define EV_SYN 0x00
39 #define EV_KEY 0x01
[all …]
/openbmc/qemu/include/standard-headers/linux/
H A Dinput-event-codes.h23 #define INPUT_PROP_POINTER 0x00 /* needs a pointer */
24 #define INPUT_PROP_DIRECT 0x01 /* direct input devices */
25 #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
26 #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
27 #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
28 #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
29 #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
31 #define INPUT_PROP_MAX 0x1f
38 #define EV_SYN 0x00
39 #define EV_KEY 0x01
[all …]
/openbmc/linux/include/dt-bindings/input/
H A Dlinux-event-codes.h23 #define INPUT_PROP_POINTER 0x00 /* needs a pointer */
24 #define INPUT_PROP_DIRECT 0x01 /* direct input devices */
25 #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
26 #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
27 #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */
28 #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */
29 #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */
31 #define INPUT_PROP_MAX 0x1f
38 #define EV_SYN 0x00
39 #define EV_KEY 0x0
[all...]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dp_types.h33 LANE_COUNT_UNKNOWN = 0,
49 LINK_RATE_UNKNOWN = 0,
50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
[all …]
/openbmc/linux/drivers/net/ieee802154/
H A Dmrf24j40.c20 #define REG_RXMCR 0x00 /* Receive MAC control */
21 #define BIT_PROMI BIT(0)
26 #define REG_PANIDL 0x01 /* PAN ID (low) */
27 #define REG_PANIDH 0x02 /* PAN ID (high) */
28 #define REG_SADRL 0x03 /* Short address (low) */
29 #define REG_SADRH 0x04 /* Short address (high) */
30 #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
31 #define REG_EADR1 0x06
32 #define REG_EADR2 0x07
33 #define REG_EADR3 0x08
[all …]
/openbmc/linux/arch/powerpc/xmon/
H A Dspu-insns.h17 0 3 1 1 2 3 0 1 1 2 3
18 0 7 4 1 0 7 4 1
23 0 9 1 2 3 0 7 1 2 3
29 0 8 2 3 0 6 2 3
35 0 1 1 2 3 0 6 8 2 3
36 0 7 4 1 4 1
41 0 1 1 1 2 3
42 0 5 7 4 1
47 …t field other than op are defined as 0s. For example, opcode of fma instruction which is RRR forma…
48 since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b000…
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
[all …]
/openbmc/linux/include/drm/display/
H A Ddrm_dp.h44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
50 #define DP_MSA_MISC_6_BPC (0 << 5)
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos_hdmi.c54 #define HDMI_MAPPED_BASE 0xffff0000
162 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
163 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
164 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
165 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
171 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
172 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
173 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
174 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
180 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.c58 #define MC_CG_ARB_FREQ_F0 0x0a
59 #define MC_CG_ARB_FREQ_F1 0x0b
60 #define MC_CG_ARB_FREQ_F2 0x0c
61 #define MC_CG_ARB_FREQ_F3 0x0d
63 #define SMC_RAM_END 0x40000
69 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
70 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
71 …{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9…
75 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
76 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dcore.h22 #define MASKBYTE0 0xff
23 #define MASKBYTE1 0xff00
24 #define MASKBYTE2 0xff0000
25 #define MASKBYTE3 0xff000000
26 #define MASKBYTE4 0xff00000000ULL
27 #define MASKHWORD 0xffff0000
28 #define MASKLWORD 0x0000ffff
29 #define MASKDWORD 0xffffffff
30 #define RFREG_MASK 0xfffff
31 #define INV_RF_DATA 0xffffffff
[all …]
/openbmc/linux/drivers/net/ethernet/realtek/
H A Dr8169_main.c64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
75 #define OCP_STD_PHY_BASE 0xa400
146 { PCI_VDEVICE(REALTEK, 0x2502) },
147 { PCI_VDEVICE(REALTEK, 0x2600) },
148 { PCI_VDEVICE(REALTEK, 0x8129) },
149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
150 { PCI_VDEVICE(REALTEK, 0x8161) },
151 { PCI_VDEVICE(REALTEK, 0x8162) },
152 { PCI_VDEVICE(REALTEK, 0x8167) },
153 { PCI_VDEVICE(REALTEK, 0x8168) },
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dci_dpm.c38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
43 #define SMC_RAM_END 0x40000
51 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
52 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
53 …{ 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9…
58 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
59 …{ 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD,…
[all …]

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