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/openbmc/linux/arch/powerpc/boot/
H A Dgamecube-head.S28 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
42 li 8, 0
43 mtspr 0x210, 8 /* IBAT0U */
44 mtspr 0x212, 8 /* IBAT1U */
45 mtspr 0x214, 8 /* IBAT2U */
46 mtspr 0x216, 8 /* IBAT3U */
47 mtspr 0x218, 8 /* DBAT0U */
48 mtspr 0x21a, 8 /* DBAT1U */
49 mtspr 0x21c, 8 /* DBAT2U */
50 mtspr 0x21e, 8 /* DBAT3U */
[all …]
H A Dwii-head.S29 rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
43 li 8, 0
44 mtspr 0x210, 8 /* IBAT0U */
45 mtspr 0x212, 8 /* IBAT1U */
46 mtspr 0x214, 8 /* IBAT2U */
47 mtspr 0x216, 8 /* IBAT3U */
48 mtspr 0x218, 8 /* DBAT0U */
49 mtspr 0x21a, 8 /* DBAT1U */
50 mtspr 0x21c, 8 /* DBAT2U */
51 mtspr 0x21e, 8 /* DBAT3U */
[all …]
/openbmc/linux/drivers/scsi/qedi/
H A Dqedi_nvm_iscsi_cfg.h37 union nvm_iscsi_ipv4_addr addr; /* 0x0 */
38 union nvm_iscsi_ipv4_addr subnet_mask; /* 0x4 */
39 union nvm_iscsi_ipv4_addr gateway; /* 0x8 */
40 union nvm_iscsi_ipv4_addr primary_dns; /* 0xC */
41 union nvm_iscsi_ipv4_addr secondary_dns; /* 0x10 */
42 union nvm_iscsi_ipv4_addr dhcp_addr; /* 0x14 */
44 union nvm_iscsi_ipv4_addr isns_server; /* 0x18 */
45 union nvm_iscsi_ipv4_addr slp_server; /* 0x1C */
46 union nvm_iscsi_ipv4_addr primay_radius_server; /* 0x20 */
47 union nvm_iscsi_ipv4_addr secondary_radius_server; /* 0x24 */
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v6_20.h9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80
16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
19 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/cbus/
H A Dutil_csr.h10 #define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
11 #define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
12 #define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
14 #define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
16 #define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
17 #define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
18 #define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
19 #define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
21 #define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
22 #define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
/openbmc/linux/Documentation/userspace-api/ioctl/
H A Dioctl-decoding.rst24 7-0 function #
28 So for example 0x82187201 is a read with arg length of 0x218,
/openbmc/linux/Documentation/input/
H A Dgameport-programming.rst16 Make sure struct gameport is initialized to 0 in all other fields. The
22 0x201 address is smaller.
24 E.g. if your driver supports addresses 0x200, 0x208, 0x210 and 0x218, then
25 0x218 would be the address of first choice.
28 space (is above 0x1000), use that one, and don't map the ISA mirror.
52 my_mmio = 0xff;
79 for (i = 0; i < 4; i++)
81 buttons[0] = my_mmio[4];
169 outb(0xff, io) will be used.
183 read function. It should fill axes[0..3] with four values of the joystick axes
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/openbmc/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_register.h10 #define L2SW_SW_INT_STATUS_0 0x0
11 #define L2SW_SW_INT_MASK_0 0x4
12 #define L2SW_FL_CNTL_TH 0x8
13 #define L2SW_CPU_FL_CNTL_TH 0xc
14 #define L2SW_PRI_FL_CNTL 0x10
15 #define L2SW_VLAN_PRI_TH 0x14
16 #define L2SW_EN_TOS_BUS 0x18
17 #define L2SW_TOS_MAP0 0x1c
18 #define L2SW_TOS_MAP1 0x20
19 #define L2SW_TOS_MAP2 0x24
[all …]
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr_regs.h11 u32 mstr ; /* 0x0 Master*/
12 u32 stat; /* 0x4 Operating Mode Status*/
13 u8 reserved008[0x10 - 0x8];
14 u32 mrctrl0; /* 0x10 Control 0.*/
15 u32 mrctrl1; /* 0x14 Control 1*/
16 u32 mrstat; /* 0x18 Status*/
17 u32 reserved01c; /* 0x1c */
18 u32 derateen; /* 0x20 Temperature Derate Enable*/
19 u32 derateint; /* 0x24 Temperature Derate Interval*/
20 u8 reserved028[0x30 - 0x28];
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpucfg.h17 u32 rst; /* base + 0x0 */
18 u32 ctrl; /* base + 0x4 */
19 u32 status; /* base + 0x8 */
20 u8 res[0x34]; /* base + 0xc */
24 u8 res0[0x40]; /* 0x000 */
25 struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
26 u8 res1[0x44]; /* 0x140 */
27 u32 gen_ctrl; /* 0x184 */
28 u32 l2_status; /* 0x188 */
29 u8 res2[0x4]; /* 0x18c */
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h14 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
15 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
17 #define RVU_PF_VF_BAR4_ADDR (0x10)
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
[all …]
/openbmc/u-boot/include/
H A Dfsl_sfp.h37 u32 ospr; /* 0x200 */
38 u32 ospr1; /* 0x204 */
40 u32 fswpr; /* 0x218 FSL Section Write Protect */
41 u32 fsl_uid; /* 0x21c FSL UID 0 */
42 u32 fsl_uid_1; /* 0x220 FSL UID 0 */
44 u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
45 u32 oem_uid; /* 0x274 OEM UID 0*/
46 u32 oem_uid_1; /* 0x278 OEM UID 1*/
47 u32 oem_uid_2; /* 0x27c OEM UID 2*/
48 u32 oem_uid_3; /* 0x280 OEM UID 3*/
[all …]
/openbmc/linux/drivers/clk/meson/
H A Dg12a.h20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
[all …]
/openbmc/linux/drivers/media/common/b2c2/
H A Dflexcop-reg.h11 FLEXCOP_UNK = 0,
18 FC_UNK = 0,
32 FC_USB = 0,
47 #define fc_data_Tag_ID_DVB 0x3e
48 #define fc_data_Tag_ID_ATSC 0x3f
49 #define fc_data_Tag_ID_IDSB 0x8b
51 #define fc_key_code_default 0x1
52 #define fc_key_code_even 0x2
53 #define fc_key_code_odd 0x3
64 FC_WRITE = 0,
[all …]
/openbmc/linux/sound/soc/fsl/
H A Dfsl_audmix.h15 #define FSL_AUDMIX_CTR 0x200 /* Control */
16 #define FSL_AUDMIX_STR 0x204 /* Status */
18 #define FSL_AUDMIX_ATCR0 0x208 /* Attenuation Control */
19 #define FSL_AUDMIX_ATIVAL0 0x20c /* Attenuation Initial Value */
20 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
21 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
22 #define FSL_AUDMIX_ATSTPTGT0 0x218 /* Attenuation step target */
23 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
24 #define FSL_AUDMIX_ATSTP0 0x220 /* Attenuation step number */
26 #define FSL_AUDMIX_ATCR1 0x228 /* Attenuation Control */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-stv0991/
H A Dstv0991_creg.h11 u32 version; /* offset 0x0 */
12 u32 hdpctl; /* offset 0x4 */
13 u32 hdpval; /* offset 0x8 */
14 u32 hdpgposet; /* offset 0xc */
15 u32 hdpgpoclr; /* offset 0x10 */
16 u32 hdpgpoval; /* offset 0x14 */
17 u32 stm_mux; /* offset 0x18 */
18 u32 sysctrl_1; /* offset 0x1c */
19 u32 sysctrl_2; /* offset 0x20 */
20 u32 sysctrl_3; /* offset 0x24 */
[all …]
/openbmc/u-boot/include/linux/mtd/
H A Domap_gpmc.h11 #define GPMC_BUF_EMPTY 0
17 OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
34 u32 config1; /* 0x00 */
35 u32 config2; /* 0x04 */
36 u32 config3; /* 0x08 */
37 u32 config4; /* 0x0C */
38 u32 config5; /* 0x10 */
39 u32 config6; /* 0x14 */
40 u32 config7; /* 0x18 */
41 u32 nand_cmd; /* 0x1C */
[all …]
/openbmc/u-boot/drivers/ata/
H A Dsata_sil3114.h29 unsigned char port_no; /* primary=0, secondary=1 */
34 /* 0-port is not available */
39 #define ATA_CMD_STANDBY 0xE2
40 #define ATA_CMD_STANDBYNOW1 0xE0
41 #define ATA_CMD_IDLE 0xE3
42 #define ATA_CMD_IDLEIMMEDIATE 0xE1
47 #define SIL_VEND_ID 0x1095
48 #define SIL3114_DEVICE_ID 0x3114
51 #define VND_SYSCONFSTAT 0x88 /* System Configuration Status and Command */
59 #define VND_SCONTROL_CH0 0x100
[all …]
/openbmc/linux/drivers/watchdog/
H A Dmachzwd.c44 #define ZF_IOBASE 0x218
45 #define INDEX 0x218
46 #define DATA_B 0x219
47 #define DATA_W 0x21A
48 #define DATA_D 0x21A
51 #define ZFL_VERSION 0x02 /* 16 */
52 #define CONTROL 0x10 /* 16 */
53 #define STATUS 0x12 /* 8 */
54 #define COUNTER_1 0x0C /* 16 */
55 #define COUNTER_2 0x0E /* 8 */
[all …]
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8135-apmixedsys.c38 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
39 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
40 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2…
41 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23…
42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, …
43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
45 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
46 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
47 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]

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