/openbmc/linux/sound/soc/qcom/ |
H A D | lpass-sc7280.c | 114 int chan = 0; in sc7280_lpass_alloc_dma_channel() 193 return 0; in sc7280_lpass_free_dma_channel() 210 for (i = 0; i < drvdata->num_clks; i++) in sc7280_lpass_init() 225 return 0; in sc7280_lpass_init() 233 return 0; in sc7280_lpass_exit() 248 return 0; in sc7280_lpass_dev_suspend() 256 .i2sctrl_reg_base = 0x1000, 257 .i2sctrl_reg_stride = 0x1000, 259 .irq_reg_base = 0x9000, 260 .irq_reg_stride = 0x1000, [all …]
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H A D | lpass-sc7180.c | 80 int chan = 0; in sc7180_lpass_alloc_dma_channel() 120 return 0; in sc7180_lpass_free_dma_channel() 137 for (i = 0; i < drvdata->num_clks; i++) in sc7180_lpass_init() 152 return 0; in sc7180_lpass_init() 160 return 0; in sc7180_lpass_exit() 175 return 0; in sc7180_lpass_dev_suspend() 183 .i2sctrl_reg_base = 0x1000, 184 .i2sctrl_reg_stride = 0x1000, 186 .irq_reg_base = 0x9000, 187 .irq_reg_stride = 0x1000, [all …]
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/openbmc/qemu/tests/qemu-iotests/ |
H A D | 046 | 25 seq=`basename $0` 34 trap "_cleanup; exit \$status" 0 1 2 3 15 60 local pattern=0 61 local cur_sec=0 63 for ((i=0;i<=$((sectors - 1));i++)); do 71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io 84 aio_write -P 10 0x18000 0x2000 87 aio_write -P 11 0x12000 0x2000 88 aio_write -P 12 0x1c000 0x2000 98 aio_write -P 20 0x28000 0x2000 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/ata/ |
H A D | fsl-sata.txt | 13 1 for controller @ 0x18000 14 2 for controller @ 0x19000 15 3 for controller @ 0x1a000 16 4 for controller @ 0x1b000 24 reg = <0x18000 0x1000>;
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/openbmc/linux/arch/powerpc/boot/dts/fsl/ |
H A D | pq3-sata2-0.dtsi | 2 * PQ3 SATAv2 device tree stub [ controller @ offset 0x18000 ] 37 reg = <0x18000 0x1000>; 39 interrupts = <74 0x2 0 0>;
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H A D | b4si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x200000 */ 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 66 pcie@0 { 71 reg = <0 0 0 0 0>; 72 interrupts = <20 2 0 0>; [all …]
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/openbmc/u-boot/doc/uImage.FIT/ |
H A D | multi_spl.its | 19 #address-cells = <0x1>; 28 load = <0x4a000000>; 36 load = <0x18000>; 37 entry = <0x18000>; 45 load = <0x40000>; 52 load = <0x4fa00000>; 60 load = <0x4fa00000>; 68 load = <0x40080000>; 76 load = <0x4fe00000>;
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/openbmc/linux/drivers/media/common/b2c2/ |
H A D | flexcop-sram.c | 28 return 0; in flexcop_sram_init() 55 return 0; in flexcop_sram_set_dest() 75 #if 0 81 for (i = 0; i < len; i++) { 82 command = bank | addr | 0x04000000 | (*buf << 0x10); 86 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) { 91 if (retries == 0) 94 write_reg_dw(adapter, 0x700, command); 106 for (i = 0; i < len; i++) { 107 command = bank | addr | 0x04008000; [all …]
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/openbmc/linux/sound/pci/au88x0/ |
H A D | au88x0_a3d.h | 18 #define HRTF_SZ 0x38 19 #define DLINE_SZ 0x28 48 #define A3D_A_HrtfCurrent 0x18000 /* 56 ULONG */ 49 #define A3D_A_GainCurrent 0x180E0 50 #define A3D_A_GainTarget 0x180E4 51 #define A3D_A_A12Current 0x180E8 /* Atmospheric current. */ 52 #define A3D_A_A21Target 0x180EC /* Atmospheric target */ 53 #define A3D_A_B01Current 0x180F0 /* Atmospheric current */ 54 #define A3D_A_B10Target 0x180F4 /* Atmospheric target */ 55 #define A3D_A_B2Current 0x180F8 /* Atmospheric current */ [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-mx6/ |
H A D | imx-regs.h | 11 #define ROMCP_ARB_BASE_ADDR 0x00000000 12 #define ROMCP_ARB_END_ADDR 0x000FFFFF 15 #define GPU_2D_ARB_BASE_ADDR 0x02200000 16 #define GPU_2D_ARB_END_ADDR 0x02203FFF 17 #define OPENVG_ARB_BASE_ADDR 0x02204000 18 #define OPENVG_ARB_END_ADDR 0x02207FFF 20 #define CAAM_ARB_BASE_ADDR 0x00100000 21 #define CAAM_ARB_END_ADDR 0x00107FFF 22 #define GPU_ARB_BASE_ADDR 0x01800000 23 #define GPU_ARB_END_ADDR 0x01803FFF [all …]
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/openbmc/linux/arch/arm/boot/dts/marvell/ |
H A D | armada-390.dtsi | 19 reg = <0x18000 0x20>;
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H A D | armada-398.dtsi | 19 reg = <0x18000 0x20>; 24 reg = <0xe0000 0x2000>;
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H A D | armada-395.dtsi | 19 reg = <0x18000 0x20>; 24 reg = <0xa8000 0x2000>; 32 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
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/openbmc/u-boot/include/configs/ |
H A D | sama5d4ek.h | 15 #define CONFIG_SYS_SDRAM_BASE 0x20000000 16 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 19 #define CONFIG_SYS_INIT_SP_ADDR 0x218000 25 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 30 #define CONFIG_SYS_NAND_BASE 0x80000000 39 #define CONFIG_SPL_TEXT_BASE 0x200000 40 #define CONFIG_SPL_MAX_SIZE 0x18000 41 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 42 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 43 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 [all …]
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H A D | sama5d4_xplained.h | 15 #define CONFIG_SYS_SDRAM_BASE 0x20000000 16 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 19 #define CONFIG_SYS_INIT_SP_ADDR 0x218000 25 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 30 #define CONFIG_SYS_NAND_BASE 0x80000000 39 #define CONFIG_SPL_TEXT_BASE 0x200000 40 #define CONFIG_SPL_MAX_SIZE 0x18000 41 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 42 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 43 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 [all …]
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H A D | axs10x.h | 13 #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 14 #define ARC_APB_PERIPHERAL_BASE 0xF0000000 15 #define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) 16 #define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) 23 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 28 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 32 #define CONFIG_SYS_LOAD_ADDR 0x82000000 56 "fatload mmc 0:1 ${loadaddr} u-boot-update.img && " \ 60 "; fi\0"
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H A D | sama5d3_xplained.h | 26 #define CONFIG_SYS_SDRAM_BASE 0x20000000 27 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 30 #define CONFIG_SYS_INIT_SP_ADDR 0x318000 39 #define CONFIG_SYS_NAND_BASE 0x60000000 53 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000 58 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 61 #define CONFIG_SPL_TEXT_BASE 0x300000 62 #define CONFIG_SPL_MAX_SIZE 0x18000 63 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 64 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 [all …]
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H A D | sama5d3xek.h | 29 #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 33 #define CONFIG_SYS_FLASH_BASE 0x10000000 39 #define CONFIG_SYS_SDRAM_BASE 0x20000000 40 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 43 #define CONFIG_SYS_INIT_SP_ADDR 0x318000 54 #define CONFIG_SYS_NAND_BASE 0x60000000 72 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 75 #define CONFIG_SPL_TEXT_BASE 0x300000 76 #define CONFIG_SPL_MAX_SIZE 0x18000 77 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
H A D | ccf.txt | 42 reg = <0x18000 0x1000>;
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | jpeg_v4_0_3.h | 27 #define regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff 28 #define regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x404d 29 #define regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x404e 30 #define regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x404f 31 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ab 32 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ac 33 #define regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40a4 34 #define regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40a6 35 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40b6 36 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40b7 [all …]
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H A D | jpeg_v2_0.h | 27 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff 28 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029 29 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a 30 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b 31 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea 32 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb 33 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf 34 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1 35 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8 36 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9 [all …]
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/openbmc/u-boot/configs/ |
H A D | dra7xx_hs_evm_defconfig | 5 CONFIG_SYS_MALLOC_F_LEN=0x18000 7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 41 CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 58 CONFIG_FASTBOOT_BUF_ADDR=0x82000000 59 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 75 CONFIG_SF_DEFAULT_MODE=0 109 CONFIG_USB_GADGET_VENDOR_NUM=0x0451 110 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
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H A D | dra7xx_evm_defconfig | 4 CONFIG_SYS_MALLOC_F_LEN=0x18000 37 CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 54 CONFIG_FASTBOOT_BUF_ADDR=0x82000000 55 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 71 CONFIG_SF_DEFAULT_MODE=0 105 CONFIG_USB_GADGET_VENDOR_NUM=0x0451 106 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
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H A D | dra7xx_hs_evm_usb_defconfig | 5 CONFIG_SYS_MALLOC_F_LEN=0x18000 7 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 8 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 9 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 10 CONFIG_ISW_ENTRY_ADDR=0x40306d50 46 CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 62 CONFIG_FASTBOOT_BUF_ADDR=0x82000000 63 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 79 CONFIG_SF_DEFAULT_MODE=0 114 CONFIG_USB_GADGET_VENDOR_NUM=0x0451 [all …]
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/ |
H A D | nv04.c | 50 nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); in nv04_instobj_wr32() 58 return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); in nv04_instobj_rd32() 77 return device->pri + 0x700000 + iobj->node->offset; in nv04_instobj_acquire() 136 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); in nv04_instobj_new() 148 return nvkm_rd32(imem->subdev.device, 0x700000 + addr); in nv04_instmem_rd32() 154 nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); in nv04_instmem_wr32() 167 ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); in nv04_instmem_oneinit() 171 /* 0x00000-0x10000: reserve for probable vbios image */ in nv04_instmem_oneinit() 172 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, in nv04_instmem_oneinit() 177 /* 0x10000-0x18000: reserve for RAMHT */ in nv04_instmem_oneinit() [all …]
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