1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 27ca6f363SBo Shen /* 37ca6f363SBo Shen * Configuration settings for the SAMA5D3 Xplained board. 47ca6f363SBo Shen * 57ca6f363SBo Shen * Copyright (C) 2014 Atmel Corporation 67ca6f363SBo Shen * Bo Shen <voice.shen@atmel.com> 77ca6f363SBo Shen */ 87ca6f363SBo Shen 97ca6f363SBo Shen #ifndef __CONFIG_H 107ca6f363SBo Shen #define __CONFIG_H 117ca6f363SBo Shen 12b2d387bcSWu, Josh #include "at91-sama5_common.h" 137ca6f363SBo Shen 147ca6f363SBo Shen /* 157ca6f363SBo Shen * This needs to be defined for the OHCI code to work but it is defined as 167ca6f363SBo Shen * ATMEL_ID_UHPHS in the CPU specific header files. 177ca6f363SBo Shen */ 18e61ed48fSWenyou Yang #define ATMEL_ID_UHP 32 197ca6f363SBo Shen 207ca6f363SBo Shen /* 217ca6f363SBo Shen * Specify the clock enable bit in the PMC_SCER register. 227ca6f363SBo Shen */ 23e61ed48fSWenyou Yang #define ATMEL_PMC_UHP (1 << 6) 247ca6f363SBo Shen 257ca6f363SBo Shen /* SDRAM */ 26e61ed48fSWenyou Yang #define CONFIG_SYS_SDRAM_BASE 0x20000000 277ca6f363SBo Shen #define CONFIG_SYS_SDRAM_SIZE 0x10000000 287ca6f363SBo Shen 29cd23aac4SBo Shen #ifdef CONFIG_SPL_BUILD 301878804aSWenyou Yang #define CONFIG_SYS_INIT_SP_ADDR 0x318000 31cd23aac4SBo Shen #else 327ca6f363SBo Shen #define CONFIG_SYS_INIT_SP_ADDR \ 331878804aSWenyou Yang (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 34cd23aac4SBo Shen #endif 357ca6f363SBo Shen 367ca6f363SBo Shen /* NAND flash */ 377ca6f363SBo Shen #ifdef CONFIG_CMD_NAND 387ca6f363SBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE 1 39e61ed48fSWenyou Yang #define CONFIG_SYS_NAND_BASE 0x60000000 407ca6f363SBo Shen /* our ALE is AD21 */ 417ca6f363SBo Shen #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 427ca6f363SBo Shen /* our CLE is AD22 */ 437ca6f363SBo Shen #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 447ca6f363SBo Shen #define CONFIG_SYS_NAND_ONFI_DETECTION 458f1a80e9STom Rini #endif 467ca6f363SBo Shen 477ca6f363SBo Shen /* USB */ 487ca6f363SBo Shen #ifdef CONFIG_CMD_USB 497ca6f363SBo Shen #define CONFIG_USB_ATMEL 507ca6f363SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 517ca6f363SBo Shen #define CONFIG_USB_OHCI_NEW 527ca6f363SBo Shen #define CONFIG_SYS_USB_OHCI_CPU_INIT 53e61ed48fSWenyou Yang #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000 547ca6f363SBo Shen #define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" 557ca6f363SBo Shen #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 567ca6f363SBo Shen #endif 577ca6f363SBo Shen 587ca6f363SBo Shen #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 597ca6f363SBo Shen 60cd23aac4SBo Shen /* SPL */ 61cd23aac4SBo Shen #define CONFIG_SPL_TEXT_BASE 0x300000 621878804aSWenyou Yang #define CONFIG_SPL_MAX_SIZE 0x18000 63cd23aac4SBo Shen #define CONFIG_SPL_BSS_START_ADDR 0x20000000 64cd23aac4SBo Shen #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 65cd23aac4SBo Shen #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 66cd23aac4SBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 67cd23aac4SBo Shen 68cd23aac4SBo Shen #define CONFIG_SYS_MONITOR_LEN (512 << 10) 69cd23aac4SBo Shen 705541543fSWenyou Yang #ifdef CONFIG_SD_BOOT 71e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 72205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 73cd23aac4SBo Shen 745541543fSWenyou Yang #elif CONFIG_NAND_BOOT 75cd23aac4SBo Shen #define CONFIG_SPL_NAND_DRIVERS 76cd23aac4SBo Shen #define CONFIG_SPL_NAND_BASE 775541543fSWenyou Yang #endif 78cd23aac4SBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 79cd23aac4SBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE 80cd23aac4SBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 81cd23aac4SBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT 64 82cd23aac4SBo Shen #define CONFIG_SYS_NAND_OOBSIZE 64 83cd23aac4SBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 84cd23aac4SBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 85cd23aac4SBo Shen 86cd23aac4SBo Shen #endif 87