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/openbmc/u-boot/doc/device-tree-bindings/leds/
H A Dleds-bcm6328.txt5 However, on some devices there are Serial LEDs (LEDs connected to a 74x164
6 controller), which can either be controlled by software (exporting the 74x164
7 as spi-gpio. See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
10 exporting the 74x164 as spi-gpio prevents those LEDs to be hardware
16 - #size-cells : must be 0.
34 - reg : LED pin number (only LEDs 0 to 23 are valid).
46 #size-cells = <0>;
47 reg = <0x10000800 0x24>;
70 #size-cells = <0>;
71 reg = <0x10001900 0x24>;
H A Dleds-bcm6358.txt4 In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller),
5 which can either be controlled by software (exporting the 74x164 as spi-gpio.
6 See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
12 - #size-cells : must be 0.
24 - reg : LED pin number (only LEDs 0 to 31 are valid).
36 #size-cells = <0>;
37 reg = <0xfffe00d0 0x8>;
40 reg = <0>;
65 #size-cells = <0>;
66 reg = <0x100000d0 0x8>;
[all …]
/openbmc/u-boot/drivers/gpio/
H A D74x164_gpio.c3 * Take drivers/gpio/gpio-74x164.c as reference.
68 return (priv->buffer[bank] >> pin) & 0x1; in gen_74x164_get_value()
88 return 0; in gen_74x164_set_value()
110 desc->offset = args->args[0]; in gen_74x164_xlate()
111 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; in gen_74x164_xlate()
113 return 0; in gen_74x164_xlate()
141 * Documentation/devicetree/bindings/gpio/gpio-74x164.txt in gen_74x164_probe()
155 ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe, in gen_74x164_probe()
170 return 0; in gen_74x164_probe()
184 U_BOOT_DRIVER(74x164) = {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/leds/
H A Dleds-bcm6358.txt4 In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller),
5 which can either be controlled by software (exporting the 74x164 as spi-gpio.
12 - #size-cells : must be 0.
24 - reg : LED pin number (only LEDs 0 to 31 are valid).
40 #size-cells = <0>;
41 reg = <0xfffe00d0 0x8>;
44 reg = <0>;
69 #size-cells = <0>;
70 reg = <0x100000d0 0x8>;
75 reg = <0>;
H A Dleds-bcm6328.yaml15 However, on some devices there are Serial LEDs (LEDs connected to a 74x164
16 controller), which can either be controlled by software (exporting the 74x164
21 exporting the 74x164 as spi-gpio prevents those LEDs to be hardware
26 with 0 meaning hardware control enabled and 1 hardware control disabled. This
67 const: 0
79 description: LED pin number (only LEDs 0 to 23 are valid).
95 signals can get muxed into these LEDs. Only valid for LEDs 0 to 7,
96 where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and signals 4 to
106 hardware signals can get muxed into these LEDs. Only valid for LEDs 0
107 to 7, where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and
[all …]
/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-firmware.c34 /* DL_ADDR_LB=0 DL_ADDR_HB=0 */ in start_fw_load()
35 cx25840_write(client, 0x800, 0x00); in start_fw_load()
36 cx25840_write(client, 0x801, 0x00); in start_fw_load()
37 // DL_MAP=3 DL_AUTO_INC=0 DL_ENABLE=1 in start_fw_load()
38 cx25840_write(client, 0x803, 0x0b); in start_fw_load()
40 cx25840_write(client, 0x000, 0x20); in start_fw_load()
45 /* AUTO_INC_DIS=0 */ in end_fw_load()
46 cx25840_write(client, 0x000, 0x00); in end_fw_load()
47 /* DL_ENABLE=0 */ in end_fw_load()
48 cx25840_write(client, 0x803, 0x03); in end_fw_load()
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v3.h10 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
12 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
13 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
14 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
15 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
16 #define QSERDES_V3_TX_TX_BAND 0x02c
17 #define QSERDES_V3_TX_SLEW_CNTL 0x030
18 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
19 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v6.h9 #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08
10 #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c
11 #define QSERDES_V6_TX_TX_DRV_LVL 0x14
12 #define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c
13 #define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20
14 #define QSERDES_V6_TX_TX_BAND 0x24
15 #define QSERDES_V6_TX_INTERFACE_SELECT 0x2c
16 #define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34
17 #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38
18 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v6.h11 #define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00
12 #define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04
13 #define QSERDES_V6_COM_CP_CTRL_MODE1 0x10
14 #define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14
15 #define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18
16 #define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c
17 #define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20
18 #define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24
19 #define QSERDES_V6_COM_DEC_START_MODE1 0x28
20 #define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-74x164.c49 ret = (chip->buffer[bank] >> pin) & 0x1; in gen_74x164_get_value()
97 return 0; in gen_74x164_direction_output()
112 if (ret < 0) in gen_74x164_probe()
158 return 0; in gen_74x164_probe()
170 gpiod_set_value_cansleep(chip->gpiod_oe, 0); in gen_74x164_remove()
191 .name = "74x164",
202 MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
/openbmc/linux/drivers/clk/mstar/
H A Dclk-msc313-cpupll.c17 * 0x140 -- LPF low. Seems to store one half of the clock transition
18 * 0x144 /
19 * 0x148 -- LPF high. Seems to store one half of the clock transition
20 * 0x14c /
21 * 0x150 -- vendor code says "toggle lpf enable"
22 * 0x154 -- mu?
23 * 0x15c -- lpf_update_count?
24 * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank?
25 * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to
27 * 0x174 -- Seems to be the PLL lock status bit
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/openbmc/linux/drivers/devfreq/event/
H A Dexynos-nocp.h13 NOCP_ID_REVISION_ID = 0x04,
14 NOCP_MAIN_CTL = 0x08,
15 NOCP_CFG_CTL = 0x0C,
17 NOCP_STAT_PERIOD = 0x24,
18 NOCP_STAT_GO = 0x28,
19 NOCP_STAT_ALARM_MIN = 0x2C,
20 NOCP_STAT_ALARM_MAX = 0x30,
21 NOCP_STAT_ALARM_STATUS = 0x34,
22 NOCP_STAT_ALARM_CLR = 0x38,
24 NOCP_COUNTERS_0_SRC = 0x138,
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/openbmc/linux/drivers/media/platform/mediatek/jpeg/
H A Dmtk_jpeg_enc_hw.h15 #define JPEG_ENC_INT_STATUS_DONE BIT(0)
16 #define JPEG_ENC_INT_STATUS_MASK_ALLIRQ 0x13
18 #define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
20 #define JPEG_ENC_CTRL_YUV_FORMAT_MASK 0x18
24 #define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
25 #define JPEG_ENC_RESET_BIT BIT(0)
27 #define JPEG_ENC_YUV_FORMAT_YUYV 0
32 #define JPEG_ENC_QUALITY_Q60 0x0
33 #define JPEG_ENC_QUALITY_Q80 0x1
34 #define JPEG_ENC_QUALITY_Q90 0x2
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h18 #define HHI_GP0_PLL_CNTL 0x40
19 #define HHI_GP0_PLL_CNTL2 0x44
20 #define HHI_GP0_PLL_CNTL3 0x48
21 #define HHI_GP0_PLL_CNTL4 0x4c
22 #define HHI_GP0_PLL_CNTL5 0x50
23 #define HHI_GP0_PLL_STS 0x54
24 #define HHI_GP0_PLL_CNTL1 0x58
25 #define HHI_HIFI_PLL_CNTL 0x80
26 #define HHI_HIFI_PLL_CNTL2 0x84
27 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
/openbmc/linux/drivers/clk/meson/
H A Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3188.c14 #define RK3188_PULL_OFFSET 0x164
15 #define RK3188_PULL_PMU_OFFSET 0x64
24 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
43 * pin in bits 1:0 in rk3188_calc_pull_reg_and_bit()
51 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
62 .grf_mux_offset = 0x60,
/openbmc/linux/drivers/net/wan/
H A Dslic_ds26522.h10 #define DS26522_RF_ADDR_START 0x00
11 #define DS26522_RF_ADDR_END 0xef
12 #define DS26522_GLB_ADDR_START 0xf0
13 #define DS26522_GLB_ADDR_END 0xff
14 #define DS26522_TF_ADDR_START 0x100
15 #define DS26522_TF_ADDR_END 0x1ef
16 #define DS26522_LIU_ADDR_START 0x1000
17 #define DS26522_LIU_ADDR_END 0x101f
18 #define DS26522_TEST_ADDR_START 0x1008
19 #define DS26522_TEST_ADDR_END 0x101f
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-esdhc.h27 #define ESDHC_HOST_CONTROL_LE 0x20
34 #define ESDHC_PRSSTAT 0x24
35 #define ESDHC_CLOCK_GATE_OFF 0x00000080
36 #define ESDHC_CLOCK_STABLE 0x00000008
39 #define ESDHC_PROCTL 0x28
40 #define ESDHC_VOLT_SEL 0x00000400
41 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
42 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
43 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
44 #define ESDHC_HOST_CONTROL_RES 0x01
[all …]
/openbmc/linux/drivers/gpu/drm/ci/xfails/
H A Drockchip-rk3288-skips.txt14 # rockchip-drm display-subsystem: [drm] *ERROR* [CRTC:35:crtc-0] commit wait timed out
21 # CPU: 3 PID: 482 Comm: kms_plane_lowre Tainted: G W 5.19.0-rc2-323596-g00535de92171…
23 # Process kms_plane_lowre (pid: 482, stack limit = 0x1193ac2b)
24 # spin_dump from do_raw_spin_lock+0xa4/0xe8
25 # do_raw_spin_lock from wait_for_completion_timeout+0x2c/0x120
26 # wait_for_completion_timeout from drm_crtc_commit_wait+0x18/0x7c
27 # drm_crtc_commit_wait from drm_atomic_helper_wait_for_dependencies+0x44/0x168
28 # drm_atomic_helper_wait_for_dependencies from commit_tail+0x34/0x180
29 # commit_tail from drm_atomic_helper_commit+0x164/0x18c
30 # drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe4
[all …]

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