1*78b4af31SQiufang Dai /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*78b4af31SQiufang Dai /* 3*78b4af31SQiufang Dai * Copyright (c) 2016 AmLogic, Inc. 4*78b4af31SQiufang Dai * Author: Michael Turquette <mturquette@baylibre.com> 5*78b4af31SQiufang Dai * 6*78b4af31SQiufang Dai * Copyright (c) 2017 Amlogic, inc. 7*78b4af31SQiufang Dai * Author: Qiufang Dai <qiufang.dai@amlogic.com> 8*78b4af31SQiufang Dai * 9*78b4af31SQiufang Dai */ 10*78b4af31SQiufang Dai #ifndef __AXG_H 11*78b4af31SQiufang Dai #define __AXG_H 12*78b4af31SQiufang Dai 13*78b4af31SQiufang Dai /* 14*78b4af31SQiufang Dai * Clock controller register offsets 15*78b4af31SQiufang Dai * 16*78b4af31SQiufang Dai * Register offsets from the data sheet must be multiplied by 4 before 17*78b4af31SQiufang Dai * adding them to the base address to get the right value. 18*78b4af31SQiufang Dai */ 19*78b4af31SQiufang Dai #define HHI_GP0_PLL_CNTL 0x40 20*78b4af31SQiufang Dai #define HHI_GP0_PLL_CNTL2 0x44 21*78b4af31SQiufang Dai #define HHI_GP0_PLL_CNTL3 0x48 22*78b4af31SQiufang Dai #define HHI_GP0_PLL_CNTL4 0x4c 23*78b4af31SQiufang Dai #define HHI_GP0_PLL_CNTL5 0x50 24*78b4af31SQiufang Dai #define HHI_GP0_PLL_STS 0x54 25*78b4af31SQiufang Dai #define HHI_GP0_PLL_CNTL1 0x58 26*78b4af31SQiufang Dai #define HHI_HIFI_PLL_CNTL 0x80 27*78b4af31SQiufang Dai #define HHI_HIFI_PLL_CNTL2 0x84 28*78b4af31SQiufang Dai #define HHI_HIFI_PLL_CNTL3 0x88 29*78b4af31SQiufang Dai #define HHI_HIFI_PLL_CNTL4 0x8C 30*78b4af31SQiufang Dai #define HHI_HIFI_PLL_CNTL5 0x90 31*78b4af31SQiufang Dai #define HHI_HIFI_PLL_STS 0x94 32*78b4af31SQiufang Dai #define HHI_HIFI_PLL_CNTL1 0x98 33*78b4af31SQiufang Dai 34*78b4af31SQiufang Dai #define HHI_XTAL_DIVN_CNTL 0xbc 35*78b4af31SQiufang Dai #define HHI_GCLK2_MPEG0 0xc0 36*78b4af31SQiufang Dai #define HHI_GCLK2_MPEG1 0xc4 37*78b4af31SQiufang Dai #define HHI_GCLK2_MPEG2 0xc8 38*78b4af31SQiufang Dai #define HHI_GCLK2_OTHER 0xd0 39*78b4af31SQiufang Dai #define HHI_GCLK2_AO 0xd4 40*78b4af31SQiufang Dai #define HHI_PCIE_PLL_CNTL 0xd8 41*78b4af31SQiufang Dai #define HHI_PCIE_PLL_CNTL1 0xdC 42*78b4af31SQiufang Dai #define HHI_PCIE_PLL_CNTL2 0xe0 43*78b4af31SQiufang Dai #define HHI_PCIE_PLL_CNTL3 0xe4 44*78b4af31SQiufang Dai #define HHI_PCIE_PLL_CNTL4 0xe8 45*78b4af31SQiufang Dai #define HHI_PCIE_PLL_CNTL5 0xec 46*78b4af31SQiufang Dai #define HHI_PCIE_PLL_CNTL6 0xf0 47*78b4af31SQiufang Dai #define HHI_PCIE_PLL_STS 0xf4 48*78b4af31SQiufang Dai 49*78b4af31SQiufang Dai #define HHI_MEM_PD_REG0 0x100 50*78b4af31SQiufang Dai #define HHI_VPU_MEM_PD_REG0 0x104 51*78b4af31SQiufang Dai #define HHI_VIID_CLK_DIV 0x128 52*78b4af31SQiufang Dai #define HHI_VIID_CLK_CNTL 0x12c 53*78b4af31SQiufang Dai 54*78b4af31SQiufang Dai #define HHI_GCLK_MPEG0 0x140 55*78b4af31SQiufang Dai #define HHI_GCLK_MPEG1 0x144 56*78b4af31SQiufang Dai #define HHI_GCLK_MPEG2 0x148 57*78b4af31SQiufang Dai #define HHI_GCLK_OTHER 0x150 58*78b4af31SQiufang Dai #define HHI_GCLK_AO 0x154 59*78b4af31SQiufang Dai #define HHI_SYS_CPU_CLK_CNTL1 0x15c 60*78b4af31SQiufang Dai #define HHI_SYS_CPU_RESET_CNTL 0x160 61*78b4af31SQiufang Dai #define HHI_VID_CLK_DIV 0x164 62*78b4af31SQiufang Dai #define HHI_SPICC_HCLK_CNTL 0x168 63*78b4af31SQiufang Dai 64*78b4af31SQiufang Dai #define HHI_MPEG_CLK_CNTL 0x174 65*78b4af31SQiufang Dai #define HHI_VID_CLK_CNTL 0x17c 66*78b4af31SQiufang Dai #define HHI_TS_CLK_CNTL 0x190 67*78b4af31SQiufang Dai #define HHI_VID_CLK_CNTL2 0x194 68*78b4af31SQiufang Dai #define HHI_SYS_CPU_CLK_CNTL0 0x19c 69*78b4af31SQiufang Dai #define HHI_VID_PLL_CLK_DIV 0x1a0 70*78b4af31SQiufang Dai #define HHI_VPU_CLK_CNTL 0x1bC 71*78b4af31SQiufang Dai 72*78b4af31SQiufang Dai #define HHI_VAPBCLK_CNTL 0x1F4 73*78b4af31SQiufang Dai 74*78b4af31SQiufang Dai #define HHI_GEN_CLK_CNTL 0x228 75*78b4af31SQiufang Dai 76*78b4af31SQiufang Dai #define HHI_VDIN_MEAS_CLK_CNTL 0x250 77*78b4af31SQiufang Dai #define HHI_NAND_CLK_CNTL 0x25C 78*78b4af31SQiufang Dai #define HHI_SD_EMMC_CLK_CNTL 0x264 79*78b4af31SQiufang Dai 80*78b4af31SQiufang Dai #define HHI_MPLL_CNTL 0x280 81*78b4af31SQiufang Dai #define HHI_MPLL_CNTL2 0x284 82*78b4af31SQiufang Dai #define HHI_MPLL_CNTL3 0x288 83*78b4af31SQiufang Dai #define HHI_MPLL_CNTL4 0x28C 84*78b4af31SQiufang Dai #define HHI_MPLL_CNTL5 0x290 85*78b4af31SQiufang Dai #define HHI_MPLL_CNTL6 0x294 86*78b4af31SQiufang Dai #define HHI_MPLL_CNTL7 0x298 87*78b4af31SQiufang Dai #define HHI_MPLL_CNTL8 0x29C 88*78b4af31SQiufang Dai #define HHI_MPLL_CNTL9 0x2A0 89*78b4af31SQiufang Dai #define HHI_MPLL_CNTL10 0x2A4 90*78b4af31SQiufang Dai 91*78b4af31SQiufang Dai #define HHI_MPLL3_CNTL0 0x2E0 92*78b4af31SQiufang Dai #define HHI_MPLL3_CNTL1 0x2E4 93*78b4af31SQiufang Dai #define HHI_PLL_TOP_MISC 0x2E8 94*78b4af31SQiufang Dai 95*78b4af31SQiufang Dai #define HHI_SYS_PLL_CNTL1 0x2FC 96*78b4af31SQiufang Dai #define HHI_SYS_PLL_CNTL 0x300 97*78b4af31SQiufang Dai #define HHI_SYS_PLL_CNTL2 0x304 98*78b4af31SQiufang Dai #define HHI_SYS_PLL_CNTL3 0x308 99*78b4af31SQiufang Dai #define HHI_SYS_PLL_CNTL4 0x30c 100*78b4af31SQiufang Dai #define HHI_SYS_PLL_CNTL5 0x310 101*78b4af31SQiufang Dai #define HHI_SYS_PLL_STS 0x314 102*78b4af31SQiufang Dai #define HHI_DPLL_TOP_I 0x318 103*78b4af31SQiufang Dai #define HHI_DPLL_TOP2_I 0x31C 104*78b4af31SQiufang Dai 105*78b4af31SQiufang Dai #endif /* __AXG_H */ 106