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Searched +full:0 +full:x05e00000 (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/arch/arm/dts/
H A Dhi6220-hikey.dts11 /memreserve/ 0x05e00000 0x00100000;
30 memory@0 {
32 reg = <0x0 0x0 0x0 0x40000000>;
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,qcm2290-mdss.yaml45 "^display-controller@[0-9a-f]+$":
51 "^dsi@[0-9a-f]+$":
57 "^phy@[0-9a-f]+$":
81 reg = <0x05e00000 0x1000>;
96 iommus = <&apps_smmu 0x420 0x2>,
97 <&apps_smmu 0x421 0x0>;
102 reg = <0x05e01000 0x8f000>,
103 <0x05eb0000 0x2008>;
117 interrupts = <0>;
121 #size-cells = <0>;
[all …]
H A Dqcom,sm6115-mdss.yaml33 "^display-controller@[0-9a-f]+$":
39 "^dsi@[0-9a-f]+$":
51 "^phy@[0-9a-f]+$":
74 reg = <0x05e00000 0x1000>;
85 iommus = <&apps_smmu 0x420 0x2>,
86 <&apps_smmu 0x421 0x0>;
91 reg = <0x05e01000 0x8f000>,
92 <0x05eb0000 0x2008>;
107 interrupts = <0>;
111 #size-cells = <0>;
[all …]
H A Dqcom,sm6375-mdss.yaml44 "^display-controller@[0-9a-f]+$":
50 "^dsi@[0-9a-f]+$":
58 "^phy@[0-9a-f]+$":
76 reg = <0x05e00000 0x1000>;
90 iommus = <&apps_smmu 0x820 0x2>;
97 reg = <0x05e01000 0x8e030>,
98 <0x05eb0000 0x2008>;
123 interrupts = <0>;
127 #size-cells = <0>;
129 port@0 {
[all …]
H A Dqcom,sm6125-mdss.yaml44 "^display-controller@[0-9a-f]+$":
50 "^dsi@[0-9a-f]+$":
58 "^phy@[0-9a-f]+$":
76 reg = <0x05e00000 0x1000>;
92 iommus = <&apps_smmu 0x400 0x0>;
100 reg = <0x05e01000 0x83208>,
101 <0x05eb0000 0x2008>;
105 interrupts = <0>;
129 #size-cells = <0>;
131 port@0 {
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-tangier/acpi/
H A Dsouthcluster.asl13 Name (_ADR, 0)
14 Name (_BBN, 0)
20 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
22 /* IO Region 0 */
24 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
27 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
31 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
36 0x00000000, 0x000ddcc0, 0x000ddccf, 0x00000000,
37 0x00000010, , , GP00)
39 /* PSH Memory Region 0 */
[all …]
/openbmc/u-boot/board/hisilicon/hikey/
H A Dhikey.c25 { 0, HI6220_GPIO_BASE(0)},
49 { "gpio_hi6220", &hi6220_gpio[0] },
95 .virt = 0x0UL,
96 .phys = 0x0UL,
97 .size = 0x80000000UL,
101 .virt = 0x80000000UL,
102 .phys = 0x80000000UL,
103 .size = 0x80000000UL,
109 0,
130 return 0; in board_uart_init()
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dsunxvr500.c58 ep->width = of_getintprop_default(ep->of_node, "width", 0); in e3d_get_props()
59 ep->height = of_getintprop_default(ep->of_node, "height", 0); in e3d_get_props()
68 return 0; in e3d_get_props()
72 * 0x04000000, the following video layout register values:
74 * RAMDAC_VID_WH 0x03ff04ff
75 * RAMDAC_VID_CFG 0x1a0b0088
76 * RAMDAC_VID_32FB_0 0x04000000
77 * RAMDAC_VID_32FB_1 0x04800000
78 * RAMDAC_VID_8FB_0 0x05000000
79 * RAMDAC_VID_8FB_1 0x05200000
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-hikey.dts32 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
33 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
34 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
35 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
36 * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
37 * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
39 memory@0 {
41 reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
42 <0x00000000 0x05f00000 0x00000000 0x00001000>,
43 <0x00000000 0x05f02000 0x00000000 0x00efd000>,
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm6115.dtsi27 #clock-cells = <0>;
32 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
44 clocks = <&cpufreq_hw 0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
62 reg = <0x0 0x1>;
63 clocks = <&cpufreq_hw 0>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]