Searched +full:0 +full:x01e20000 (Results 1 – 15 of 15) sorted by relevance
24 #define EMAC_BASE_ADDR 0x5C01000025 #define EMAC_WRAPPER_BASE_ADDR 0x5C00000026 #define EMAC_WRAPPER_RAM_ADDR 0x5C02000027 #define EMAC_MDIO_BASE_ADDR 0x5C03000028 #define EMAC_HW_RAM_ADDR 0x01E20000
28 #define DA8XX_TPCC_BASE 0x01c0000029 #define DA8XX_TPTC0_BASE 0x01c0800030 #define DA8XX_TPTC1_BASE 0x01c0840031 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */32 #define DA8XX_I2C0_BASE 0x01c2200033 #define DA8XX_RTC_BASE 0x01c2300034 #define DA8XX_PRUSS_MEM_BASE 0x01c3000035 #define DA8XX_MMCSD0_BASE 0x01c4000036 #define DA8XX_SPI0_BASE 0x01c4100037 #define DA830_SPI1_BASE 0x01e12000[all …]
64 "^iommu-ctx@[0-9a-f]+$":109 reg = <0x01ef0000 0x3000>;117 ranges = <0 0x01e20000 0x40000>;122 reg = <0x4000 0x1000>;
11 #define SUNXI_SRAM_A1_BASE 0x0000000014 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */20 #define SUNXI_DE2_BASE 0x0100000023 #define SUNXI_CPUCFG_BASE 0x0170000026 #define SUNXI_SRAMC_BASE 0x01c0000027 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
35 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)36 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)37 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)38 #define DAVINCI_UART0_BASE (0x01c20000)39 #define DAVINCI_UART1_BASE (0x01c20400)40 #define DAVINCI_TIMER3_BASE (0x01c20800)41 #define DAVINCI_I2C_BASE (0x01c21000)42 #define DAVINCI_TIMER0_BASE (0x01c21400)43 #define DAVINCI_TIMER1_BASE (0x01c21800)44 #define DAVINCI_WDOG_BASE (0x01c21c00)[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;195 reg = <0x01c00000 0x30>;200 sram_a: sram@0 {202 reg = <0x00000000 0xc000>;205 ranges = <0 0x00000000 0xc000>;209 reg = <0x8000 0x4000>;[all …]
65 framebuffer@0 {100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;161 reg = <0x40000000 0x80000000>;184 #clock-cells = <0>;190 osc32k: clk@0 {191 #clock-cells = <0>;207 #clock-cells = <0>;214 #clock-cells = <0>;[all …]
65 simplefb_hdmi: framebuffer@0 {100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;170 reg = <0x40000000 0x80000000>;187 #clock-cells = <0>;192 osc32k: clk@0 {193 #clock-cells = <0>;209 #clock-cells = <0>;216 #clock-cells = <0>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;213 #clock-cells = <0>;221 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;252 #clock-cells = <0>;254 reg = <0x01c200d0 0x4>;274 reg = <0x01c02000 0x1000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]
25 #clock-cells = <0>;31 #clock-cells = <0>;39 #size-cells = <0>;41 CPU0: cpu@0 {44 reg = <0x0>;54 reg = <0x1>;64 reg = <0x2>;74 reg = <0x3>;84 reg = <0x100>;94 reg = <0x101>;[all …]
29 #clock-cells = <0>;35 #clock-cells = <0>;42 #size-cells = <0>;48 reg = <0x100>;66 reg = <0x101>;79 reg = <0x102>;92 reg = <0x103>;101 CPU4: cpu@0 {105 reg = <0x0>;123 reg = <0x1>;[all …]
26 reg = <0 0x80000000 0 0>;35 reg = <0x0 0x86000000 0x0 0x300000>;41 reg = <0x0 0x86300000 0x0 0x100000>;49 reg = <0x0 0x86400000 0x0 0x100000>;54 reg = <0x0 0x86500000 0x0 0x180000>;59 reg = <0x0 0x86680000 0x0 0x80000>;65 reg = <0x0 0x86700000 0x0 0xe0000>;72 reg = <0x0 0x867e0000 0x0 0x20000>;77 reg = <0x0 0x86800000 0x0 0x2b00000>;82 reg = <0x0 0x89300000 0x0 0x600000>;[all …]
11 * 0-5 A number of folks worked on this driver in bits and pieces but the major64 module_param(debug_level, int, 0);92 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */93 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */94 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */95 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */96 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */97 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */98 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */99 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */[all …]