11  * 0-5 A number of folks worked on this driver in bits and pieces but the major
64 module_param(debug_level, int, 0);
92 #define EMAC_DEF_PASS_CRC		(0) /* Do not pass CRC up to frames */
93 #define EMAC_DEF_QOS_EN			(0) /* EMAC proprietary QoS disabled */
94 #define EMAC_DEF_NO_BUFF_CHAIN		(0) /* No buffer chain */
95 #define EMAC_DEF_MACCTRL_FRAME_EN	(0) /* Discard Maccontrol frames */
96 #define EMAC_DEF_SHORT_FRAME_EN		(0) /* Discard short frames */
97 #define EMAC_DEF_ERROR_FRAME_EN		(0) /* Discard error frames */
98 #define EMAC_DEF_PROM_EN		(0) /* Promiscuous disabled */
99 #define EMAC_DEF_PROM_CH		(0) /* Promiscuous channel is 0 */
101 #define EMAC_DEF_BCAST_CH		(0) /* Broadcast channel is 0 */
103 #define EMAC_DEF_MCAST_CH		(0) /* Multicast channel is 0 */
106 #define EMAC_DEF_TXPACING_EN		(0) /* TX pacing NOT supported*/
108 #define EMAC_DEF_BUFFER_OFFSET		(0) /* Buffer offset to DMA (future) */
111 #define EMAC_DEF_TX_CH			(0) /* Default 0th channel */
112 #define EMAC_DEF_RX_CH			(0) /* Default 0th channel */
122 #define EMAC_ALL_MULTI_REG_VALUE	(0xFFFFFFFF)
124 #define EMAC_TX_CONTROL_TX_ENABLE_VAL	(0x1)
125 #define EMAC_RX_CONTROL_RX_ENABLE_VAL	(0x1)
126 #define EMAC_MAC_HOST_ERR_INTMASK_VAL	(0x2)
127 #define EMAC_RX_UNICAST_CLEAR_ALL	(0xFF)
128 #define EMAC_INT_MASK_CLEAR		(0xFF)
139 #define EMAC_RXMBP_PROMCH_MASK		(0x7 << 16)
142 #define EMAC_RXMBP_BROADCH_MASK		(0x7 << 8)
144 #define EMAC_RXMBP_MULTICH_SHIFT	(0)
145 #define EMAC_RXMBP_MULTICH_MASK		(0x7)
146 #define EMAC_RXMBP_CHMASK		(0x7)
149 # define EMAC_MBP_RXPROMISC		(0x00200000)
150 # define EMAC_MBP_PROMISCCH(ch)		(((ch) & 0x7) << 16)
151 # define EMAC_MBP_RXBCAST		(0x00002000)
152 # define EMAC_MBP_BCASTCHAN(ch)		(((ch) & 0x7) << 8)
153 # define EMAC_MBP_RXMCAST		(0x00000020)
154 # define EMAC_MBP_MCASTCHAN(ch)		((ch) & 0x7)
161 #define EMAC_MACCONTROL_FULLDUPLEXEN	BIT(0)
169 #define EMAC_MACSTATUS_TXERRCODE_MASK	(0xF00000)
171 #define EMAC_MACSTATUS_TXERRCH_MASK	(0x70000)
173 #define EMAC_MACSTATUS_RXERRCODE_MASK	(0xF000)
175 #define EMAC_MACSTATUS_RXERRCH_MASK	(0x700)
179 #define EMAC_RX_MAX_LEN_MASK		(0xFFFF)
180 #define EMAC_RX_BUFFER_OFFSET_MASK	(0xFFFF)
182 /* MAC_IN_VECTOR (0x180) register bit fields */
186 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC	BIT(0)
201 #define EMAC_RX_BD_BUF_SIZE		(0xFFFF)
203 #define EMAC_RX_BD_PKT_LENGTH_MASK	(0xFFFF)
210 #define EMAC_MACINVECTOR	0x90
212 #define EMAC_DM646X_MACEOIVECTOR	0x94
214 #define EMAC_MACINTSTATRAW	0xB0
215 #define EMAC_MACINTSTATMASKED	0xB4
216 #define EMAC_MACINTMASKSET	0xB8
217 #define EMAC_MACINTMASKCLEAR	0xBC
219 #define EMAC_RXMBPENABLE	0x100
220 #define EMAC_RXUNICASTSET	0x104
221 #define EMAC_RXUNICASTCLEAR	0x108
222 #define EMAC_RXMAXLEN		0x10C
223 #define EMAC_RXBUFFEROFFSET	0x110
224 #define EMAC_RXFILTERLOWTHRESH	0x114
226 #define EMAC_MACCONTROL		0x160
227 #define EMAC_MACSTATUS		0x164
228 #define EMAC_EMCONTROL		0x168
229 #define EMAC_FIFOCONTROL	0x16C
230 #define EMAC_MACCONFIG		0x170
231 #define EMAC_SOFTRESET		0x174
232 #define EMAC_MACSRCADDRLO	0x1D0
233 #define EMAC_MACSRCADDRHI	0x1D4
234 #define EMAC_MACHASH1		0x1D8
235 #define EMAC_MACHASH2		0x1DC
236 #define EMAC_MACADDRLO		0x500
237 #define EMAC_MACADDRHI		0x504
238 #define EMAC_MACINDEX		0x508
241 #define EMAC_RXGOODFRAMES	0x200
242 #define EMAC_RXBCASTFRAMES	0x204
243 #define EMAC_RXMCASTFRAMES	0x208
244 #define EMAC_RXPAUSEFRAMES	0x20C
245 #define EMAC_RXCRCERRORS	0x210
246 #define EMAC_RXALIGNCODEERRORS	0x214
247 #define EMAC_RXOVERSIZED	0x218
248 #define EMAC_RXJABBER		0x21C
249 #define EMAC_RXUNDERSIZED	0x220
250 #define EMAC_RXFRAGMENTS	0x224
251 #define EMAC_RXFILTERED		0x228
252 #define EMAC_RXQOSFILTERED	0x22C
253 #define EMAC_RXOCTETS		0x230
254 #define EMAC_TXGOODFRAMES	0x234
255 #define EMAC_TXBCASTFRAMES	0x238
256 #define EMAC_TXMCASTFRAMES	0x23C
257 #define EMAC_TXPAUSEFRAMES	0x240
258 #define EMAC_TXDEFERRED		0x244
259 #define EMAC_TXCOLLISION	0x248
260 #define EMAC_TXSINGLECOLL	0x24C
261 #define EMAC_TXMULTICOLL	0x250
262 #define EMAC_TXEXCESSIVECOLL	0x254
263 #define EMAC_TXLATECOLL		0x258
264 #define EMAC_TXUNDERRUN		0x25C
265 #define EMAC_TXCARRIERSENSE	0x260
266 #define EMAC_TXOCTETS		0x264
267 #define EMAC_NETOCTETS		0x280
268 #define EMAC_RXSOFOVERRUNS	0x284
269 #define EMAC_RXMOFOVERRUNS	0x288
270 #define EMAC_RXDMAOVERRUNS	0x28C
273 #define EMAC_CTRL_EWCTL		(0x4)
274 #define EMAC_CTRL_EWINTTCNT	(0x8)
277 #define EMAC_DM644X_EWINTCNT_MASK	0x1FFFF
278 #define EMAC_DM644X_INTMIN_INTVL	0x1
282 #define EMAC_DM646X_CMINTCTRL	0x0C
283 #define EMAC_DM646X_CMRXINTEN	0x14
284 #define EMAC_DM646X_CMTXINTEN	0x18
285 #define EMAC_DM646X_CMRXINTMAX	0x70
286 #define EMAC_DM646X_CMTXINTMAX	0x74
289 #define EMAC_DM646X_INTPACEEN		(0x3 << 16)
290 #define EMAC_DM646X_INTPRESCALE_MASK	(0x7FF << 0)
298 #define EMAC_DM646X_MAC_EOI_C0_RXEN	(0x01)
299 #define EMAC_DM646X_MAC_EOI_C0_TXEN	(0x02)
302 #define EMAC_STATS_CLR_MASK    (0xFFFFFFFF)
321 	u32 link; /* 1=link on, 0=link off */
322 	u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
323 	u32 duplex; /* Link duplex: 0=Half, 1=Full */
399 	return 0;  in emac_get_coalesce()
419 	u32 int_ctrl, num_interrupts = 0;  in emac_set_coalesce()
420 	u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;  in emac_set_coalesce()
423 		priv->coal_intvl = 0;  in emac_set_coalesce()
427 			emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0);  in emac_set_coalesce()
430 			emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0);  in emac_set_coalesce()
434 		return 0;  in emac_set_coalesce()
493 	return 0;  in emac_set_coalesce()
591 	hash = 0;  in hash_get()
593 	for (cnt = 0; cnt < 2; cnt++) {  in hash_get()
602 	return hash & 0x3F;  in hash_get()
616 	u32 rc = 0;  in emac_hash_add()
630 	if (priv->multicast_hash_cnt[hash_value] == 0) {  in emac_hash_add()
661 	if (priv->multicast_hash_cnt[hash_value] > 0) {  in emac_hash_del()
666 	/* if counter still > 0, at least one multicast address refers  in emac_hash_del()
667 	 * to this hash bit. so return 0 */  in emac_hash_del()
668 	if (priv->multicast_hash_cnt[hash_value] > 0)  in emac_hash_del()
669 		return 0;  in emac_hash_del()
684 #define EMAC_MULTICAST_ADD	0
717 		priv->mac_hash1 = 0;  in emac_add_mcast()
718 		priv->mac_hash2 = 0;  in emac_add_mcast()
719 		memset(&(priv->multicast_hash_cnt[0]), 0,  in emac_add_mcast()
720 		sizeof(priv->multicast_hash_cnt[0]) *  in emac_add_mcast()
731 	if (update > 0) {  in emac_add_mcast()
798 		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);  in emac_int_disable()
799 		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);  in emac_int_disable()
818 		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);  in emac_int_disable()
835 		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);  in emac_int_enable()
836 		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);  in emac_int_enable()
845 		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);  in emac_int_enable()
898 	if (status < 0) {  in emac_rx_handler()
920 			skb_tailroom(skb), 0);  in emac_rx_handler()
923 	if (unlikely(ret < 0))  in emac_rx_handler()
966 	if (unlikely(ret_code < 0)) {  in emac_dev_xmit()
975 				     0);  in emac_dev_xmit()
976 	if (unlikely(ret_code != 0)) {  in emac_dev_xmit()
1030  * Returns success (0) or appropriate error code (none as of now)
1039 	       (mac_addr[1] << 8) | (mac_addr[0]));  in emac_set_type0addr()
1057  * Returns success (0) or appropriate error code (none as of now)
1066 	       (mac_addr[1] << 8) | (mac_addr[0]));  in emac_set_type1addr()
1081  * Returns success (0) or appropriate error code (none as of now)
1089 	       (mac_addr[1] << 8) | (mac_addr[0]));  in emac_set_type2addr()
1091 	val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \  in emac_set_type2addr()
1105  * Returns success (0) or appropriate error code (none as of now)
1111 	if (priv->rx_addr_type == 0) {  in emac_setmac()
1115 		for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)  in emac_setmac()
1133  * Returns success (0) or appropriate error code (none as of now)
1157 	return 0;  in emac_dev_setmac_addr()
1167  * Returns success (0) or appropriate error code (none right now)
1183 		(((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |  in emac_hw_enable()
1184 		((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |  in emac_hw_enable()
1185 		((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |  in emac_hw_enable()
1186 		((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));  in emac_hw_enable()
1190 		(((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |  in emac_hw_enable()
1191 		((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |  in emac_hw_enable()
1192 		 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |  in emac_hw_enable()
1193 		 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |  in emac_hw_enable()
1194 		 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |  in emac_hw_enable()
1195 		 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |  in emac_hw_enable()
1196 		 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |  in emac_hw_enable()
1199 		 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |  in emac_hw_enable()
1202 		 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |  in emac_hw_enable()
1210 	emac_write(EMAC_RXFILTERLOWTHRESH, 0);  in emac_hw_enable()
1212 	priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;  in emac_hw_enable()
1226 	return 0;  in emac_hw_enable()
1249 	u32 status = 0;  in emac_poll()
1250 	u32 num_rx_pkts = 0;  in emac_poll()
1291 					&emac_txhost_errcodes[cause][0], ch);  in emac_poll()
1301 					&emac_rxhost_errcodes[cause][0], ch);  in emac_poll()
1334 	int new_state = 0;  in emac_adjust_link()
1355 		priv->link = 0;  in emac_adjust_link()
1356 		priv->speed = 0;  in emac_adjust_link()
1357 		priv->duplex = ~0;  in emac_adjust_link()
1379  * Returns success(0) or appropriate error code
1411  * Returns 0 for a successful open, or appropriate error code
1418 	int res_num = 0, irq_num = 0;  in emac_dev_open()
1419 	int i = 0;  in emac_dev_open()
1425 	if (ret < 0) {  in emac_dev_open()
1437 	priv->mac_hash1 = 0;  in emac_dev_open()
1438 	priv->mac_hash2 = 0;  in emac_dev_open()
1439 	emac_write(EMAC_MACHASH1, 0);  in emac_dev_open()
1440 	emac_write(EMAC_MACHASH2, 0);  in emac_dev_open()
1442 	for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {  in emac_dev_open()
1449 					     skb_tailroom(skb), 0);  in emac_dev_open()
1450 		if (WARN_ON(ret < 0))  in emac_dev_open()
1457 			if (ret < 0)  in emac_dev_open()
1460 			ret = request_irq(ret, emac_irq, 0, ndev->name, ndev);  in emac_dev_open()
1470 				ret = request_irq(irq_num, emac_irq, 0, ndev->name, ndev);  in emac_dev_open()
1487 	if (priv->coal_intvl != 0) {  in emac_dev_open()
1498 					&emac_adjust_link, 0, 0);  in emac_dev_open()
1511 		 * some systems it can be 'davinci_mdio.0' so we need to use  in emac_dev_open()
1536 		priv->link = 0;  in emac_dev_open()
1537 		priv->speed = 0;  in emac_dev_open()
1538 		priv->duplex = ~0;  in emac_dev_open()
1558 	return 0;  in emac_dev_open()
1566 		for (q = res_num - 1; q >= 0; q--) {  in emac_dev_open()
1568 			if (irq_num > 0)  in emac_dev_open()
1572 		for (q = res_num; q >= 0; q--) {  in emac_dev_open()
1601 	int i = 0;  in emac_dev_stop()
1605 	int ret = 0;  in emac_dev_stop()
1623 			if (ret < 0 && ret != -ENXIO)  in emac_dev_stop()
1625 			if (ret > 0) {  in emac_dev_stop()
1628 				ret = 0;  in emac_dev_stop()
1663 	if (err < 0) {  in emac_dev_getnetstats()
1676 		stats_clear_mask = 0;  in emac_dev_getnetstats()
1768 	priv->phy_node = of_parse_phandle(np, "phy-handle", 0);  in davinci_emac_of_get_pdata()
1772 		else if (of_phy_register_fixed_link(np) >= 0)  in davinci_emac_of_get_pdata()
1812 	int rc = 0;  in davinci_emac_probe()
1861 	priv->coal_intvl = 0;  in davinci_emac_probe()
1865 	priv->remap_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in davinci_emac_probe()
1891 	memset(&dma_params, 0, sizeof(dma_params));  in davinci_emac_probe()
1894 	dma_params.rxthresh		= priv->emac_base + 0x120;  in davinci_emac_probe()
1895 	dma_params.rxfree		= priv->emac_base + 0x140;  in davinci_emac_probe()
1896 	dma_params.txhdp		= priv->emac_base + 0x600;  in davinci_emac_probe()
1897 	dma_params.rxhdp		= priv->emac_base + 0x620;  in davinci_emac_probe()
1898 	dma_params.txcp			= priv->emac_base + 0x640;  in davinci_emac_probe()
1899 	dma_params.rxcp			= priv->emac_base + 0x660;  in davinci_emac_probe()
1906 	dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :  in davinci_emac_probe()
1917 					 emac_tx_handler, 0);  in davinci_emac_probe()
1932 	rc = platform_get_irq(pdev, 0);  in davinci_emac_probe()
1933 	if (rc < 0)  in davinci_emac_probe()
1937 	rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);  in davinci_emac_probe()
1955 	if (rc < 0) {  in davinci_emac_probe()
1979 	return 0;  in davinci_emac_probe()
2026 	return 0;  in davinci_emac_remove()
2036 	return 0;  in davinci_emac_suspend()
2046 	return 0;  in davinci_emac_resume()
2056 	.hw_ram_addr		= 0x01e20000,