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/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf201.dts67 reg = <0x4d>;
82 mount-matrix = "-1", "0", "0",
83 "0", "-1", "0",
84 "0", "0", "-1";
88 mount-matrix = "0", "-1", "0",
89 "-1", "0", "0",
90 "0", "0", "-1";
95 mount-matrix = "1", "0", "0",
96 "0", "-1", "0",
97 "0", "0", "1";
[all …]
H A Dtegra30-pegatron-chagall.dts49 reg = <0x80000000 0x40000000>;
59 alloc-ranges = <0x80000000 0x30000000>;
60 size = <0x10000000>; /* 256MiB */
67 reg = <0xbeb00000 0x10000>; /* 64kB */
68 console-size = <0x8000>; /* 32kB */
69 record-size = <0x400>; /* 1kB */
74 reg = <0xbfe00000 0x200000>; /* 2MB */
100 pinctrl-0 = <&state_default>;
144 nvidia,lock = <0>;
145 nvidia,io-reset = <0>;
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf700t.dts18 port@0 {
92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
[all …]
/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r2_addu_s_ph.c10 rs = 0x00FE00FE; in main()
11 rt = 0x00020001; in main()
12 result = 0x010000FF; in main()
14 ("addu_s.ph %0, %1, %2\n\t" in main()
20 rs = 0xFFFF1111; in main()
21 rt = 0x00020001; in main()
22 result = 0xFFFF1112; in main()
24 ("addu_s.ph %0, %2, %3\n\t" in main()
30 assert(((dsp >> 20) & 0x01) == 1); in main()
32 return 0; in main()
H A Dtest_dsp_r2_addu_ph.c10 rs = 0x00FF00FF; in main()
11 rt = 0x00010001; in main()
12 result = 0x01000100; in main()
14 ("addu.ph %0, %1, %2\n\t" in main()
20 rs = 0xFFFF1111; in main()
21 rt = 0x00020001; in main()
22 result = 0x00011112; in main()
24 ("addu.ph %0, %2, %3\n\t" in main()
30 assert(((dsp >> 20) & 0x01) == 1); in main()
32 return 0; in main()
H A Dtest_dsp_r1_addu_s_qb.c10 rs = 0x10FF01FF; in main()
11 rt = 0x10010001; in main()
12 result = 0x20FF01FF; in main()
14 ("addu_s.qb %0, %2, %3\n\t" in main()
20 assert(((dsp >> 20) & 0x1) == 1); in main()
22 rs = 0xFFFF1111; in main()
23 rt = 0x00020001; in main()
24 result = 0xFFFF1112; in main()
26 ("addu_s.qb %0, %2, %3\n\t" in main()
32 assert(((dsp >> 20) & 0x1) == 1); in main()
[all …]
H A Dtest_dsp_r1_addu_qb.c10 rs = 0x00FF00FF; in main()
11 rt = 0x00010001; in main()
12 result = 0x00000000; in main()
14 ("addu.qb %0, %2, %3\n\t" in main()
20 assert(((dsp >> 20) & 0x01) == 1); in main()
22 rs = 0xFFFF1111; in main()
23 rt = 0x00020001; in main()
24 result = 0xFF011112; in main()
26 ("addu.qb %0, %2, %3\n\t" in main()
32 assert(((dsp >> 20) & 0x01) == 1); in main()
[all …]
H A Dtest_dsp_r1_addwc.c10 rs = 0x10FF01FF; in main()
11 rt = 0x10010001; in main()
12 dspi = 0x00002000; in main()
13 result = 0x21000201; in main()
16 "addwc %0, %1, %2\n\t" in main()
22 rs = 0xFFFF1111; in main()
23 rt = 0x00020001; in main()
24 dspi = 0x00; in main()
25 result = 0x00011112; in main()
28 "addwc %0, %1, %2\n\t" in main()
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Drv770.c56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
71 return 0; in rv770_set_uvd_clocks()
75 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
84 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
88 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
90 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
117 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
121 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
122 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
/openbmc/qemu/hw/usb/
H A Dvt82c686-uhci-pci.c9 via_isa_set_irq(&s->dev, 0, level); in uhci_isa_set_irq()
18 pci_set_long(pci_conf + 0x40, 0x00001000); in usb_uhci_vt82c686b_realize()
20 pci_set_long(pci_conf + 0x80, 0x00020001); in usb_uhci_vt82c686b_realize()
22 pci_set_long(pci_conf + 0xc0, 0x00002000); in usb_uhci_vt82c686b_realize()
26 s->state.irq = qemu_allocate_irq(uhci_isa_set_irq, s, 0); in usb_uhci_vt82c686b_realize()
34 .revision = 0x01,
/openbmc/qemu/pc-bios/s390-ccw/
H A Dsclp.h15 #define SCLP_CMDW_READ_SCP_INFO 0x00020001
16 #define SCLP_CMDW_READ_SCP_INFO_FORCED 0x00120001
17 #define SCLP_CMD_READ_EVENT_DATA 0x00770005
18 #define SCLP_CMD_WRITE_EVENT_DATA 0x00760005
19 #define SCLP_CMD_READ_EVENT_DATA 0x00770005
20 #define SCLP_CMD_WRITE_EVENT_DATA 0x00760005
21 #define SCLP_CMD_WRITE_EVENT_MASK 0x00780005
24 #define SCLP_RC_NORMAL_READ_COMPLETION 0x0010
25 #define SCLP_RC_NORMAL_COMPLETION 0x0020
26 #define SCLP_RC_INVALID_SCLP_COMMAND 0x01f0
[all …]
/openbmc/linux/drivers/gpu/drm/vmwgfx/device_include/
H A Dsvga_overlay.h44 #define VMWARE_FOURCC_YV12 0x32315659
45 #define VMWARE_FOURCC_YUY2 0x32595559
46 #define VMWARE_FOURCC_UYVY 0x59565955
49 SVGA_OVERLAY_FORMAT_INVALID = 0,
55 #define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
57 #define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
59 #define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
61 #define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/openbmc/linux/drivers/infiniband/sw/rxe/
H A Drxe_param.h17 return 0; in rxe_mtu_int_to_enum()
41 RXE_PAGE_SIZE_CAP = 0xfffff000,
72 RXE_MAX_RES_RD_ATOM = 0x3f000,
76 RXE_MAX_TOT_MCAST_QP_ATTACH = 0x70000,
96 RXE_MIN_SRQ_INDEX = 0x00020001,
100 RXE_MIN_MR_INDEX = 0x00000001,
125 RXE_VENDOR_ID = 0XFFFFFF,
133 RXE_PORT_BAD_PKEY_CNTR = 0,
134 RXE_PORT_QKEY_VIOL_CNTR = 0,
135 RXE_PORT_LID = 0,
[all …]
/openbmc/qemu/include/hw/arm/
H A Draspberrypi-fw-defs.h15 RPI_FWREQ_PROPERTY_END = 0,
16 RPI_FWREQ_GET_FIRMWARE_REVISION = 0x00000001,
17 RPI_FWREQ_GET_FIRMWARE_VARIANT = 0x00000002,
18 RPI_FWREQ_GET_FIRMWARE_HASH = 0x00000003,
20 RPI_FWREQ_SET_CURSOR_INFO = 0x00008010,
21 RPI_FWREQ_SET_CURSOR_STATE = 0x00008011,
23 RPI_FWREQ_GET_BOARD_MODEL = 0x00010001,
24 RPI_FWREQ_GET_BOARD_REVISION = 0x00010002,
25 RPI_FWREQ_GET_BOARD_MAC_ADDRESS = 0x00010003,
26 RPI_FWREQ_GET_BOARD_SERIAL = 0x00010004,
[all …]
/openbmc/linux/include/soc/bcm2835/
H A Draspberrypi-firmware.h15 RPI_FIRMWARE_STATUS_REQUEST = 0,
16 RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000,
17 RPI_FIRMWARE_STATUS_ERROR = 0x80000001,
37 RPI_FIRMWARE_PROPERTY_END = 0,
38 RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001,
40 RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010,
41 RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011,
43 RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001,
44 RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002,
45 RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003,
[all …]
/openbmc/qemu/include/hw/s390x/
H A Dsclp.h21 #define SCLP_CMD_CODE_MASK 0xffff00ff
24 #define SCLP_CMDW_READ_SCP_INFO 0x00020001
25 #define SCLP_CMDW_READ_SCP_INFO_FORCED 0x00120001
26 #define SCLP_READ_STORAGE_ELEMENT_INFO 0x00040001
27 #define SCLP_ATTACH_STORAGE_ELEMENT 0x00080001
28 #define SCLP_ASSIGN_STORAGE 0x000D0001
29 #define SCLP_UNASSIGN_STORAGE 0x000C0001
30 #define SCLP_CMD_READ_EVENT_DATA 0x00770005
31 #define SCLP_CMD_WRITE_EVENT_DATA 0x00760005
32 #define SCLP_CMD_WRITE_EVENT_MASK 0x00780005
[all …]
/openbmc/qemu/hw/ide/
H A Dvia.c50 case 0: in bmdma_read()
57 val = 0xff; in bmdma_read()
76 case 0: in bmdma_write()
96 for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) { in bmdma_setup_bar()
114 d->config[0x70 + n * 8] |= 0x80; in via_ide_set_irq()
116 d->config[0x70 + n * 8] &= ~0x80; in via_ide_set_irq()
129 for (i = 0; i < ARRAY_SIZE(d->bus); i++) { in via_ide_reset()
133 pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy mode */ in via_ide_reset()
140 pci_set_byte(pci_conf + PCI_INTERRUPT_LINE, 0xe); in via_ide_reset()
143 pci_set_long(pci_conf + 0x40, 0x0a090600); in via_ide_reset()
[all …]
/openbmc/u-boot/board/renesas/blanche/
H A Dblanche.c32 #define CPG_PLL1CR 0xE6150028
33 #define CPG_PLL3CR 0xE61500DC
50 if (cpu_type == 0x4A) { in blanche_init_sys()
51 writel(0x4D000000, CPG_PLL1CR); in blanche_init_sys()
52 writel(0x4F000000, CPG_PLL3CR); in blanche_init_sys()
56 writel(0xA5A5A500, &rwdt->rwtcsra); in blanche_init_sys()
57 writel(0xA5A5A500, &swdt->swtcsra); in blanche_init_sys()
63 { 0x0004, 0x0bffffff }, in blanche_init_pfc()
64 { 0x0008, 0x002fffff }, in blanche_init_pfc()
65 { 0x0014, 0x00000fff }, in blanche_init_pfc()
[all …]
/openbmc/u-boot/arch/arm/mach-bcm283x/include/mach/
H A Dmbox.h41 #define BCM2835_MBOX_PHYSADDR 0x3f00b880
43 #define BCM2835_MBOX_PHYSADDR 0x2000b880
54 #define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
55 #define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000
58 #define BCM2835_CHAN_MASK 0xf
74 #define BCM2835_MBOX_REQ_CODE 0
75 #define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000
78 memset((_m_), 0, sizeof(*(_m_))); \
80 (_m_)->hdr.code = 0; \
81 (_m_)->end_tag = 0; \
[all …]
/openbmc/u-boot/board/renesas/gose/
H A Dgose_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
44 u32 r0 = 0; in spl_init_sys()
46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys()
56 "orr %0, #0x1800 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/alt/
H A Dalt_spl.c26 #define SD1CKCR 0xE6150078
27 #define SD_97500KHZ 0x7
38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
44 u32 r0 = 0; in spl_init_sys()
46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys()
56 "orr %0, #0x1800 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/koelsch/
H A Dkoelsch_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
37 static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; in dbsc_wait()
39 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
42 while (!(readl(dbsc3_1_base + reg) & BIT(0))) in dbsc_wait()
48 u32 r0 = 0; in spl_init_sys()
50 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
51 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
55 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
57 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
[all …]
/openbmc/u-boot/board/renesas/lager/
H A Dlager_spl.c26 #define SD2CKCR 0xE615026C
27 #define SD_97500KHZ 0x7
38 while (!(readl(dbsc3_0_base + reg) & BIT(0))) in dbsc_wait()
44 u32 r0 = 0; in spl_init_sys()
46 writel(0xa5a5a500, 0xe6020004); in spl_init_sys()
47 writel(0xa5a5a500, 0xe6030004); in spl_init_sys()
51 "mcr 15, 0, %0, cr7, cr5, 0 \n" in spl_init_sys()
53 "mcr 15, 0, %0, cr7, cr5, 6 \n" in spl_init_sys()
55 "mrc 15, 0, %0, cr1, cr0, 0 \n" in spl_init_sys()
56 "orr %0, #0x1800 \n" in spl_init_sys()
[all …]

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