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/openbmc/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc25 XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc, 0, 0, 0, 0, 0, 0)
26 XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0, 0, 0, 0, 0, 0, 0)
27 XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1, 0, 0, 0, 0, 0, 0)
28 XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2, 0, 0, 0, 0, 0, 0)
29 XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3, 0, 0, 0, 0, 0, 0)
30 XTREG(5, 20, 32, 4, 4, 0x0104, 0x0006, -2, 1, 0x0002, ar4, 0, 0, 0, 0, 0, 0)
31 XTREG(6, 24, 32, 4, 4, 0x0105, 0x0006, -2, 1, 0x0002, ar5, 0, 0, 0, 0, 0, 0)
32 XTREG(7, 28, 32, 4, 4, 0x0106, 0x0006, -2, 1, 0x0002, ar6, 0, 0, 0, 0, 0, 0)
33 XTREG(8, 32, 32, 4, 4, 0x0107, 0x0006, -2, 1, 0x0002, ar7, 0, 0, 0, 0, 0, 0)
34 XTREG(9, 36, 32, 4, 4, 0x0108, 0x0006, -2, 1, 0x0002, ar8, 0, 0, 0, 0, 0, 0)
[all …]
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc22 XTREG(0, 0, 32, 4, 4, 0x0020, 0x0006, -2, 9, 0x0100, pc,
23 0, 0, 0, 0, 0, 0)
24 XTREG(1, 4, 32, 4, 4, 0x0100, 0x0006, -2, 1, 0x0002, ar0,
25 0, 0, 0, 0, 0, 0)
26 XTREG(2, 8, 32, 4, 4, 0x0101, 0x0006, -2, 1, 0x0002, ar1,
27 0, 0, 0, 0, 0, 0)
28 XTREG(3, 12, 32, 4, 4, 0x0102, 0x0006, -2, 1, 0x0002, ar2,
29 0, 0, 0, 0, 0, 0)
30 XTREG(4, 16, 32, 4, 4, 0x0103, 0x0006, -2, 1, 0x0002, ar3,
31 0, 0, 0, 0, 0, 0)
[all …]
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc24 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
25 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
26 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
27 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
28 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
29 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
31 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
32 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
33 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/openbmc/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/openbmc/linux/include/linux/mfd/wm8350/
H A Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
H A Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/openbmc/linux/drivers/media/i2c/s5c73m3/
H A Ds5c73m3.h44 #define AHB_MSB_ADDR_PTR 0xfcfc
45 #define REG_CMDWR_ADDRH 0x0050
46 #define REG_CMDWR_ADDRL 0x0054
47 #define REG_CMDRD_ADDRH 0x0058
48 #define REG_CMDRD_ADDRL 0x005c
49 #define REG_CMDBUF_ADDR 0x0f14
51 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52 #define SEQ_END_PLL (1<<0x0)
53 #define SEQ_END_SENSOR (1<<0x1)
54 #define SEQ_END_GPIO (1<<0x2)
[all …]
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm8903.h22 #define WM8903_SW_RESET_AND_ID 0x00
23 #define WM8903_REVISION_NUMBER 0x01
24 #define WM8903_BIAS_CONTROL_0 0x04
25 #define WM8903_VMID_CONTROL_0 0x05
26 #define WM8903_MIC_BIAS_CONTROL_0 0x06
27 #define WM8903_ANALOGUE_DAC_0 0x08
28 #define WM8903_ANALOGUE_ADC_0 0x0A
29 #define WM8903_POWER_MANAGEMENT_0 0x0C
30 #define WM8903_POWER_MANAGEMENT_1 0x0D
31 #define WM8903_POWER_MANAGEMENT_2 0x0E
[all …]
H A Dtlv320aic23.h19 #define TLV320AIC23_LINVOL 0x00
20 #define TLV320AIC23_RINVOL 0x01
21 #define TLV320AIC23_LCHNVOL 0x02
22 #define TLV320AIC23_RCHNVOL 0x03
23 #define TLV320AIC23_ANLG 0x04
24 #define TLV320AIC23_DIGT 0x05
25 #define TLV320AIC23_PWR 0x06
26 #define TLV320AIC23_DIGT_FMT 0x07
27 #define TLV320AIC23_SRATE 0x08
28 #define TLV320AIC23_ACTIVE 0x09
[all …]
/openbmc/u-boot/drivers/sound/
H A Dwm8994_registers.h12 #define WM8994_SOFTWARE_RESET 0x00
13 #define WM8994_POWER_MANAGEMENT_1 0x01
14 #define WM8994_POWER_MANAGEMENT_2 0x02
15 #define WM8994_POWER_MANAGEMENT_4 0x04
16 #define WM8994_POWER_MANAGEMENT_5 0x05
17 #define WM8994_LEFT_OUTPUT_VOLUME 0x1C
18 #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D
19 #define WM8994_OUTPUT_MIXER_1 0x2D
20 #define WM8994_OUTPUT_MIXER_2 0x2E
21 #define WM8994_CHARGE_PUMP_1 0x4C
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_emac.h57 #define AT91_EMAC_CTL_LB 0x0001
58 #define AT91_EMAC_CTL_LBL 0x0002
59 #define AT91_EMAC_CTL_RE 0x0004
60 #define AT91_EMAC_CTL_TE 0x0008
61 #define AT91_EMAC_CTL_MPE 0x0010
62 #define AT91_EMAC_CTL_CSR 0x0020
63 #define AT91_EMAC_CTL_ISR 0x0040
64 #define AT91_EMAC_CTL_WES 0x0080
65 #define AT91_EMAC_CTL_BP 0x1000
67 #define AT91_EMAC_CFG_SPD 0x0001
[all …]
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/openbmc/linux/include/sound/
H A Dwm8903.h15 #define WM8903_GPIO_CONFIG_ZERO 0x8000
18 * R6 (0x06) - Mic Bias Control 0
20 #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
23 #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
26 #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
27 #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
30 #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
31 #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
32 #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
40 #define WM8903_GPn_FN_GPIO_OUTPUT 0
[all …]
/openbmc/u-boot/include/linux/
H A Dmdio.h65 #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
66 #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
67 #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
68 #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
69 #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
70 #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
76 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
80 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001
87 #define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
88 #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
/openbmc/linux/include/linux/mfd/wm831x/
H A Dirq.h14 #define WM831X_IRQ_TEMP_THW 0
75 * R16400 (0x4010) - System Interrupts
77 #define WM831X_PS_INT 0x8000 /* PS_INT */
78 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
81 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
82 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
85 #define WM831X_GP_INT 0x2000 /* GP_INT */
86 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
89 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
90 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
/openbmc/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc24 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
25 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
26 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
27 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
28 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
29 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
30 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
31 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
32 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
33 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/openbmc/linux/include/uapi/linux/
H A Dmdio.h76 #define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
79 #define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
89 #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
90 #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
91 #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
92 #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
93 #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
94 #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
100 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
104 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001
[all …]
/openbmc/linux/sound/pci/oxygen/
H A Dcm9780.h5 #define CM9780_JACK 0x62
6 #define CM9780_MIXER 0x64
7 #define CM9780_GPIO_SETUP 0x70
8 #define CM9780_GPIO_STATUS 0x72
11 #define CM9780_RSOE 0x0001
12 #define CM9780_CBOE 0x0002
13 #define CM9780_SSOE 0x0004
14 #define CM9780_FROE 0x0008
15 #define CM9780_HP2FMICOE 0x0010
16 #define CM9780_CB2MICOE 0x0020
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_ht.h8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dps3av.h13 #define PS3AV_VERSION 0x205 /* version of ps3av command */
15 #define PS3AV_CID_AV_INIT 0x00000001
16 #define PS3AV_CID_AV_FIN 0x00000002
17 #define PS3AV_CID_AV_GET_HW_CONF 0x00000003
18 #define PS3AV_CID_AV_GET_MONITOR_INFO 0x00000004
19 #define PS3AV_CID_AV_ENABLE_EVENT 0x00000006
20 #define PS3AV_CID_AV_DISABLE_EVENT 0x00000007
21 #define PS3AV_CID_AV_TV_MUTE 0x0000000a
23 #define PS3AV_CID_AV_VIDEO_CS 0x00010001
24 #define PS3AV_CID_AV_VIDEO_MUTE 0x00010002
[all …]
/openbmc/linux/include/linux/mfd/arizona/
H A Dregisters.h16 #define ARIZONA_SOFTWARE_RESET 0x00
17 #define ARIZONA_DEVICE_REVISION 0x01
18 #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
19 #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
20 #define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A
21 #define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B
22 #define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C
23 #define ARIZONA_CTRL_IF_STATUS_1 0x0D
24 #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
25 #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
[all …]

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