1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 27d4d0a3eSMark Brown /* 37d4d0a3eSMark Brown * include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x 47d4d0a3eSMark Brown * 57d4d0a3eSMark Brown * Copyright 2009 Wolfson Microelectronics PLC. 67d4d0a3eSMark Brown * 77d4d0a3eSMark Brown * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 87d4d0a3eSMark Brown */ 97d4d0a3eSMark Brown 107d4d0a3eSMark Brown #ifndef __MFD_WM831X_IRQ_H__ 117d4d0a3eSMark Brown #define __MFD_WM831X_IRQ_H__ 127d4d0a3eSMark Brown 137d4d0a3eSMark Brown /* Interrupt number assignments within Linux */ 147d4d0a3eSMark Brown #define WM831X_IRQ_TEMP_THW 0 157d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_1 1 167d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_2 2 177d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_3 3 187d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_4 4 197d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_5 5 207d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_6 6 217d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_7 7 227d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_8 8 237d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_9 9 247d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_10 10 257d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_11 11 267d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_12 12 277d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_13 13 287d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_14 14 297d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_15 15 307d4d0a3eSMark Brown #define WM831X_IRQ_GPIO_16 16 317d4d0a3eSMark Brown #define WM831X_IRQ_ON 17 327d4d0a3eSMark Brown #define WM831X_IRQ_PPM_SYSLO 18 337d4d0a3eSMark Brown #define WM831X_IRQ_PPM_PWR_SRC 19 347d4d0a3eSMark Brown #define WM831X_IRQ_PPM_USB_CURR 20 357d4d0a3eSMark Brown #define WM831X_IRQ_WDOG_TO 21 367d4d0a3eSMark Brown #define WM831X_IRQ_RTC_PER 22 377d4d0a3eSMark Brown #define WM831X_IRQ_RTC_ALM 23 387d4d0a3eSMark Brown #define WM831X_IRQ_CHG_BATT_HOT 24 397d4d0a3eSMark Brown #define WM831X_IRQ_CHG_BATT_COLD 25 407d4d0a3eSMark Brown #define WM831X_IRQ_CHG_BATT_FAIL 26 417d4d0a3eSMark Brown #define WM831X_IRQ_CHG_OV 27 427d4d0a3eSMark Brown #define WM831X_IRQ_CHG_END 29 437d4d0a3eSMark Brown #define WM831X_IRQ_CHG_TO 30 447d4d0a3eSMark Brown #define WM831X_IRQ_CHG_MODE 31 457d4d0a3eSMark Brown #define WM831X_IRQ_CHG_START 32 467d4d0a3eSMark Brown #define WM831X_IRQ_TCHDATA 33 477d4d0a3eSMark Brown #define WM831X_IRQ_TCHPD 34 487d4d0a3eSMark Brown #define WM831X_IRQ_AUXADC_DATA 35 497d4d0a3eSMark Brown #define WM831X_IRQ_AUXADC_DCOMP1 36 507d4d0a3eSMark Brown #define WM831X_IRQ_AUXADC_DCOMP2 37 517d4d0a3eSMark Brown #define WM831X_IRQ_AUXADC_DCOMP3 38 527d4d0a3eSMark Brown #define WM831X_IRQ_AUXADC_DCOMP4 39 537d4d0a3eSMark Brown #define WM831X_IRQ_CS1 40 547d4d0a3eSMark Brown #define WM831X_IRQ_CS2 41 557d4d0a3eSMark Brown #define WM831X_IRQ_HC_DC1 42 567d4d0a3eSMark Brown #define WM831X_IRQ_HC_DC2 43 577d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO1 44 587d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO2 45 597d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO3 46 607d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO4 47 617d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO5 48 627d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO6 49 637d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO7 50 647d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO8 51 657d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO9 52 667d4d0a3eSMark Brown #define WM831X_IRQ_UV_LDO10 53 677d4d0a3eSMark Brown #define WM831X_IRQ_UV_DC1 54 687d4d0a3eSMark Brown #define WM831X_IRQ_UV_DC2 55 697d4d0a3eSMark Brown #define WM831X_IRQ_UV_DC3 56 707d4d0a3eSMark Brown #define WM831X_IRQ_UV_DC4 57 717d4d0a3eSMark Brown 727d4d0a3eSMark Brown #define WM831X_NUM_IRQS 58 737d4d0a3eSMark Brown 747d4d0a3eSMark Brown /* 757d4d0a3eSMark Brown * R16400 (0x4010) - System Interrupts 767d4d0a3eSMark Brown */ 777d4d0a3eSMark Brown #define WM831X_PS_INT 0x8000 /* PS_INT */ 787d4d0a3eSMark Brown #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */ 797d4d0a3eSMark Brown #define WM831X_PS_INT_SHIFT 15 /* PS_INT */ 807d4d0a3eSMark Brown #define WM831X_PS_INT_WIDTH 1 /* PS_INT */ 817d4d0a3eSMark Brown #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */ 827d4d0a3eSMark Brown #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */ 837d4d0a3eSMark Brown #define WM831X_TEMP_INT_SHIFT 14 /* TEMP_INT */ 847d4d0a3eSMark Brown #define WM831X_TEMP_INT_WIDTH 1 /* TEMP_INT */ 857d4d0a3eSMark Brown #define WM831X_GP_INT 0x2000 /* GP_INT */ 867d4d0a3eSMark Brown #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */ 877d4d0a3eSMark Brown #define WM831X_GP_INT_SHIFT 13 /* GP_INT */ 887d4d0a3eSMark Brown #define WM831X_GP_INT_WIDTH 1 /* GP_INT */ 897d4d0a3eSMark Brown #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */ 907d4d0a3eSMark Brown #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */ 917d4d0a3eSMark Brown #define WM831X_ON_PIN_INT_SHIFT 12 /* ON_PIN_INT */ 927d4d0a3eSMark Brown #define WM831X_ON_PIN_INT_WIDTH 1 /* ON_PIN_INT */ 937d4d0a3eSMark Brown #define WM831X_WDOG_INT 0x0800 /* WDOG_INT */ 947d4d0a3eSMark Brown #define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */ 957d4d0a3eSMark Brown #define WM831X_WDOG_INT_SHIFT 11 /* WDOG_INT */ 967d4d0a3eSMark Brown #define WM831X_WDOG_INT_WIDTH 1 /* WDOG_INT */ 977d4d0a3eSMark Brown #define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */ 987d4d0a3eSMark Brown #define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */ 997d4d0a3eSMark Brown #define WM831X_TCHDATA_INT_SHIFT 10 /* TCHDATA_INT */ 1007d4d0a3eSMark Brown #define WM831X_TCHDATA_INT_WIDTH 1 /* TCHDATA_INT */ 1017d4d0a3eSMark Brown #define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */ 1027d4d0a3eSMark Brown #define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */ 1037d4d0a3eSMark Brown #define WM831X_TCHPD_INT_SHIFT 9 /* TCHPD_INT */ 1047d4d0a3eSMark Brown #define WM831X_TCHPD_INT_WIDTH 1 /* TCHPD_INT */ 1057d4d0a3eSMark Brown #define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */ 1067d4d0a3eSMark Brown #define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */ 1077d4d0a3eSMark Brown #define WM831X_AUXADC_INT_SHIFT 8 /* AUXADC_INT */ 1087d4d0a3eSMark Brown #define WM831X_AUXADC_INT_WIDTH 1 /* AUXADC_INT */ 1097d4d0a3eSMark Brown #define WM831X_PPM_INT 0x0080 /* PPM_INT */ 1107d4d0a3eSMark Brown #define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */ 1117d4d0a3eSMark Brown #define WM831X_PPM_INT_SHIFT 7 /* PPM_INT */ 1127d4d0a3eSMark Brown #define WM831X_PPM_INT_WIDTH 1 /* PPM_INT */ 1137d4d0a3eSMark Brown #define WM831X_CS_INT 0x0040 /* CS_INT */ 1147d4d0a3eSMark Brown #define WM831X_CS_INT_MASK 0x0040 /* CS_INT */ 1157d4d0a3eSMark Brown #define WM831X_CS_INT_SHIFT 6 /* CS_INT */ 1167d4d0a3eSMark Brown #define WM831X_CS_INT_WIDTH 1 /* CS_INT */ 1177d4d0a3eSMark Brown #define WM831X_RTC_INT 0x0020 /* RTC_INT */ 1187d4d0a3eSMark Brown #define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */ 1197d4d0a3eSMark Brown #define WM831X_RTC_INT_SHIFT 5 /* RTC_INT */ 1207d4d0a3eSMark Brown #define WM831X_RTC_INT_WIDTH 1 /* RTC_INT */ 1217d4d0a3eSMark Brown #define WM831X_OTP_INT 0x0010 /* OTP_INT */ 1227d4d0a3eSMark Brown #define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */ 1237d4d0a3eSMark Brown #define WM831X_OTP_INT_SHIFT 4 /* OTP_INT */ 1247d4d0a3eSMark Brown #define WM831X_OTP_INT_WIDTH 1 /* OTP_INT */ 1257d4d0a3eSMark Brown #define WM831X_CHILD_INT 0x0008 /* CHILD_INT */ 1267d4d0a3eSMark Brown #define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */ 1277d4d0a3eSMark Brown #define WM831X_CHILD_INT_SHIFT 3 /* CHILD_INT */ 1287d4d0a3eSMark Brown #define WM831X_CHILD_INT_WIDTH 1 /* CHILD_INT */ 1297d4d0a3eSMark Brown #define WM831X_CHG_INT 0x0004 /* CHG_INT */ 1307d4d0a3eSMark Brown #define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */ 1317d4d0a3eSMark Brown #define WM831X_CHG_INT_SHIFT 2 /* CHG_INT */ 1327d4d0a3eSMark Brown #define WM831X_CHG_INT_WIDTH 1 /* CHG_INT */ 1337d4d0a3eSMark Brown #define WM831X_HC_INT 0x0002 /* HC_INT */ 1347d4d0a3eSMark Brown #define WM831X_HC_INT_MASK 0x0002 /* HC_INT */ 1357d4d0a3eSMark Brown #define WM831X_HC_INT_SHIFT 1 /* HC_INT */ 1367d4d0a3eSMark Brown #define WM831X_HC_INT_WIDTH 1 /* HC_INT */ 1377d4d0a3eSMark Brown #define WM831X_UV_INT 0x0001 /* UV_INT */ 1387d4d0a3eSMark Brown #define WM831X_UV_INT_MASK 0x0001 /* UV_INT */ 1397d4d0a3eSMark Brown #define WM831X_UV_INT_SHIFT 0 /* UV_INT */ 1407d4d0a3eSMark Brown #define WM831X_UV_INT_WIDTH 1 /* UV_INT */ 1417d4d0a3eSMark Brown 1427d4d0a3eSMark Brown /* 1437d4d0a3eSMark Brown * R16401 (0x4011) - Interrupt Status 1 1447d4d0a3eSMark Brown */ 1457d4d0a3eSMark Brown #define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */ 1467d4d0a3eSMark Brown #define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */ 1477d4d0a3eSMark Brown #define WM831X_PPM_SYSLO_EINT_SHIFT 15 /* PPM_SYSLO_EINT */ 1487d4d0a3eSMark Brown #define WM831X_PPM_SYSLO_EINT_WIDTH 1 /* PPM_SYSLO_EINT */ 1497d4d0a3eSMark Brown #define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */ 1507d4d0a3eSMark Brown #define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */ 1517d4d0a3eSMark Brown #define WM831X_PPM_PWR_SRC_EINT_SHIFT 14 /* PPM_PWR_SRC_EINT */ 1527d4d0a3eSMark Brown #define WM831X_PPM_PWR_SRC_EINT_WIDTH 1 /* PPM_PWR_SRC_EINT */ 1537d4d0a3eSMark Brown #define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */ 1547d4d0a3eSMark Brown #define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */ 1557d4d0a3eSMark Brown #define WM831X_PPM_USB_CURR_EINT_SHIFT 13 /* PPM_USB_CURR_EINT */ 1567d4d0a3eSMark Brown #define WM831X_PPM_USB_CURR_EINT_WIDTH 1 /* PPM_USB_CURR_EINT */ 1577d4d0a3eSMark Brown #define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */ 1587d4d0a3eSMark Brown #define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */ 1597d4d0a3eSMark Brown #define WM831X_ON_PIN_EINT_SHIFT 12 /* ON_PIN_EINT */ 1607d4d0a3eSMark Brown #define WM831X_ON_PIN_EINT_WIDTH 1 /* ON_PIN_EINT */ 1617d4d0a3eSMark Brown #define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */ 1627d4d0a3eSMark Brown #define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */ 1637d4d0a3eSMark Brown #define WM831X_WDOG_TO_EINT_SHIFT 11 /* WDOG_TO_EINT */ 1647d4d0a3eSMark Brown #define WM831X_WDOG_TO_EINT_WIDTH 1 /* WDOG_TO_EINT */ 1657d4d0a3eSMark Brown #define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */ 1667d4d0a3eSMark Brown #define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */ 1677d4d0a3eSMark Brown #define WM831X_TCHDATA_EINT_SHIFT 10 /* TCHDATA_EINT */ 1687d4d0a3eSMark Brown #define WM831X_TCHDATA_EINT_WIDTH 1 /* TCHDATA_EINT */ 1697d4d0a3eSMark Brown #define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */ 1707d4d0a3eSMark Brown #define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */ 1717d4d0a3eSMark Brown #define WM831X_TCHPD_EINT_SHIFT 9 /* TCHPD_EINT */ 1727d4d0a3eSMark Brown #define WM831X_TCHPD_EINT_WIDTH 1 /* TCHPD_EINT */ 1737d4d0a3eSMark Brown #define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */ 1747d4d0a3eSMark Brown #define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */ 1757d4d0a3eSMark Brown #define WM831X_AUXADC_DATA_EINT_SHIFT 8 /* AUXADC_DATA_EINT */ 1767d4d0a3eSMark Brown #define WM831X_AUXADC_DATA_EINT_WIDTH 1 /* AUXADC_DATA_EINT */ 1777d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */ 1787d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */ 1797d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP4_EINT_SHIFT 7 /* AUXADC_DCOMP4_EINT */ 1807d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP4_EINT_WIDTH 1 /* AUXADC_DCOMP4_EINT */ 1817d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */ 1827d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */ 1837d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP3_EINT_SHIFT 6 /* AUXADC_DCOMP3_EINT */ 1847d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP3_EINT_WIDTH 1 /* AUXADC_DCOMP3_EINT */ 1857d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */ 1867d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */ 1877d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP2_EINT_SHIFT 5 /* AUXADC_DCOMP2_EINT */ 1887d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP2_EINT_WIDTH 1 /* AUXADC_DCOMP2_EINT */ 1897d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */ 1907d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */ 1917d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP1_EINT_SHIFT 4 /* AUXADC_DCOMP1_EINT */ 1927d4d0a3eSMark Brown #define WM831X_AUXADC_DCOMP1_EINT_WIDTH 1 /* AUXADC_DCOMP1_EINT */ 1937d4d0a3eSMark Brown #define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */ 1947d4d0a3eSMark Brown #define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */ 1957d4d0a3eSMark Brown #define WM831X_RTC_PER_EINT_SHIFT 3 /* RTC_PER_EINT */ 1967d4d0a3eSMark Brown #define WM831X_RTC_PER_EINT_WIDTH 1 /* RTC_PER_EINT */ 1977d4d0a3eSMark Brown #define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */ 1987d4d0a3eSMark Brown #define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */ 1997d4d0a3eSMark Brown #define WM831X_RTC_ALM_EINT_SHIFT 2 /* RTC_ALM_EINT */ 2007d4d0a3eSMark Brown #define WM831X_RTC_ALM_EINT_WIDTH 1 /* RTC_ALM_EINT */ 2017d4d0a3eSMark Brown #define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */ 2027d4d0a3eSMark Brown #define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */ 2037d4d0a3eSMark Brown #define WM831X_TEMP_THW_EINT_SHIFT 1 /* TEMP_THW_EINT */ 2047d4d0a3eSMark Brown #define WM831X_TEMP_THW_EINT_WIDTH 1 /* TEMP_THW_EINT */ 2057d4d0a3eSMark Brown 2067d4d0a3eSMark Brown /* 2077d4d0a3eSMark Brown * R16402 (0x4012) - Interrupt Status 2 2087d4d0a3eSMark Brown */ 2097d4d0a3eSMark Brown #define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */ 2107d4d0a3eSMark Brown #define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */ 2117d4d0a3eSMark Brown #define WM831X_CHG_BATT_HOT_EINT_SHIFT 15 /* CHG_BATT_HOT_EINT */ 2127d4d0a3eSMark Brown #define WM831X_CHG_BATT_HOT_EINT_WIDTH 1 /* CHG_BATT_HOT_EINT */ 2137d4d0a3eSMark Brown #define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */ 2147d4d0a3eSMark Brown #define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */ 2157d4d0a3eSMark Brown #define WM831X_CHG_BATT_COLD_EINT_SHIFT 14 /* CHG_BATT_COLD_EINT */ 2167d4d0a3eSMark Brown #define WM831X_CHG_BATT_COLD_EINT_WIDTH 1 /* CHG_BATT_COLD_EINT */ 2177d4d0a3eSMark Brown #define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */ 2187d4d0a3eSMark Brown #define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */ 2197d4d0a3eSMark Brown #define WM831X_CHG_BATT_FAIL_EINT_SHIFT 13 /* CHG_BATT_FAIL_EINT */ 2207d4d0a3eSMark Brown #define WM831X_CHG_BATT_FAIL_EINT_WIDTH 1 /* CHG_BATT_FAIL_EINT */ 2217d4d0a3eSMark Brown #define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */ 2227d4d0a3eSMark Brown #define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */ 2237d4d0a3eSMark Brown #define WM831X_CHG_OV_EINT_SHIFT 12 /* CHG_OV_EINT */ 2247d4d0a3eSMark Brown #define WM831X_CHG_OV_EINT_WIDTH 1 /* CHG_OV_EINT */ 2257d4d0a3eSMark Brown #define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */ 2267d4d0a3eSMark Brown #define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */ 2277d4d0a3eSMark Brown #define WM831X_CHG_END_EINT_SHIFT 11 /* CHG_END_EINT */ 2287d4d0a3eSMark Brown #define WM831X_CHG_END_EINT_WIDTH 1 /* CHG_END_EINT */ 2297d4d0a3eSMark Brown #define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */ 2307d4d0a3eSMark Brown #define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */ 2317d4d0a3eSMark Brown #define WM831X_CHG_TO_EINT_SHIFT 10 /* CHG_TO_EINT */ 2327d4d0a3eSMark Brown #define WM831X_CHG_TO_EINT_WIDTH 1 /* CHG_TO_EINT */ 2337d4d0a3eSMark Brown #define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */ 2347d4d0a3eSMark Brown #define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */ 2357d4d0a3eSMark Brown #define WM831X_CHG_MODE_EINT_SHIFT 9 /* CHG_MODE_EINT */ 2367d4d0a3eSMark Brown #define WM831X_CHG_MODE_EINT_WIDTH 1 /* CHG_MODE_EINT */ 2377d4d0a3eSMark Brown #define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */ 2387d4d0a3eSMark Brown #define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */ 2397d4d0a3eSMark Brown #define WM831X_CHG_START_EINT_SHIFT 8 /* CHG_START_EINT */ 2407d4d0a3eSMark Brown #define WM831X_CHG_START_EINT_WIDTH 1 /* CHG_START_EINT */ 2417d4d0a3eSMark Brown #define WM831X_CS2_EINT 0x0080 /* CS2_EINT */ 2427d4d0a3eSMark Brown #define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */ 2437d4d0a3eSMark Brown #define WM831X_CS2_EINT_SHIFT 7 /* CS2_EINT */ 2447d4d0a3eSMark Brown #define WM831X_CS2_EINT_WIDTH 1 /* CS2_EINT */ 2457d4d0a3eSMark Brown #define WM831X_CS1_EINT 0x0040 /* CS1_EINT */ 2467d4d0a3eSMark Brown #define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */ 2477d4d0a3eSMark Brown #define WM831X_CS1_EINT_SHIFT 6 /* CS1_EINT */ 2487d4d0a3eSMark Brown #define WM831X_CS1_EINT_WIDTH 1 /* CS1_EINT */ 2497d4d0a3eSMark Brown #define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */ 2507d4d0a3eSMark Brown #define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */ 2517d4d0a3eSMark Brown #define WM831X_OTP_CMD_END_EINT_SHIFT 5 /* OTP_CMD_END_EINT */ 2527d4d0a3eSMark Brown #define WM831X_OTP_CMD_END_EINT_WIDTH 1 /* OTP_CMD_END_EINT */ 2537d4d0a3eSMark Brown #define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */ 2547d4d0a3eSMark Brown #define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */ 2557d4d0a3eSMark Brown #define WM831X_OTP_ERR_EINT_SHIFT 4 /* OTP_ERR_EINT */ 2567d4d0a3eSMark Brown #define WM831X_OTP_ERR_EINT_WIDTH 1 /* OTP_ERR_EINT */ 2577d4d0a3eSMark Brown #define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */ 2587d4d0a3eSMark Brown #define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */ 2597d4d0a3eSMark Brown #define WM831X_PS_POR_EINT_SHIFT 2 /* PS_POR_EINT */ 2607d4d0a3eSMark Brown #define WM831X_PS_POR_EINT_WIDTH 1 /* PS_POR_EINT */ 2617d4d0a3eSMark Brown #define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */ 2627d4d0a3eSMark Brown #define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */ 2637d4d0a3eSMark Brown #define WM831X_PS_SLEEP_OFF_EINT_SHIFT 1 /* PS_SLEEP_OFF_EINT */ 2647d4d0a3eSMark Brown #define WM831X_PS_SLEEP_OFF_EINT_WIDTH 1 /* PS_SLEEP_OFF_EINT */ 2657d4d0a3eSMark Brown #define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */ 2667d4d0a3eSMark Brown #define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */ 2677d4d0a3eSMark Brown #define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */ 2687d4d0a3eSMark Brown #define WM831X_PS_ON_WAKE_EINT_WIDTH 1 /* PS_ON_WAKE_EINT */ 2697d4d0a3eSMark Brown 2707d4d0a3eSMark Brown /* 2717d4d0a3eSMark Brown * R16403 (0x4013) - Interrupt Status 3 2727d4d0a3eSMark Brown */ 2737d4d0a3eSMark Brown #define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */ 2747d4d0a3eSMark Brown #define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */ 2757d4d0a3eSMark Brown #define WM831X_UV_LDO10_EINT_SHIFT 9 /* UV_LDO10_EINT */ 2767d4d0a3eSMark Brown #define WM831X_UV_LDO10_EINT_WIDTH 1 /* UV_LDO10_EINT */ 2777d4d0a3eSMark Brown #define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */ 2787d4d0a3eSMark Brown #define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */ 2797d4d0a3eSMark Brown #define WM831X_UV_LDO9_EINT_SHIFT 8 /* UV_LDO9_EINT */ 2807d4d0a3eSMark Brown #define WM831X_UV_LDO9_EINT_WIDTH 1 /* UV_LDO9_EINT */ 2817d4d0a3eSMark Brown #define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */ 2827d4d0a3eSMark Brown #define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */ 2837d4d0a3eSMark Brown #define WM831X_UV_LDO8_EINT_SHIFT 7 /* UV_LDO8_EINT */ 2847d4d0a3eSMark Brown #define WM831X_UV_LDO8_EINT_WIDTH 1 /* UV_LDO8_EINT */ 2857d4d0a3eSMark Brown #define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */ 2867d4d0a3eSMark Brown #define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */ 2877d4d0a3eSMark Brown #define WM831X_UV_LDO7_EINT_SHIFT 6 /* UV_LDO7_EINT */ 2887d4d0a3eSMark Brown #define WM831X_UV_LDO7_EINT_WIDTH 1 /* UV_LDO7_EINT */ 2897d4d0a3eSMark Brown #define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */ 2907d4d0a3eSMark Brown #define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */ 2917d4d0a3eSMark Brown #define WM831X_UV_LDO6_EINT_SHIFT 5 /* UV_LDO6_EINT */ 2927d4d0a3eSMark Brown #define WM831X_UV_LDO6_EINT_WIDTH 1 /* UV_LDO6_EINT */ 2937d4d0a3eSMark Brown #define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */ 2947d4d0a3eSMark Brown #define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */ 2957d4d0a3eSMark Brown #define WM831X_UV_LDO5_EINT_SHIFT 4 /* UV_LDO5_EINT */ 2967d4d0a3eSMark Brown #define WM831X_UV_LDO5_EINT_WIDTH 1 /* UV_LDO5_EINT */ 2977d4d0a3eSMark Brown #define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */ 2987d4d0a3eSMark Brown #define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */ 2997d4d0a3eSMark Brown #define WM831X_UV_LDO4_EINT_SHIFT 3 /* UV_LDO4_EINT */ 3007d4d0a3eSMark Brown #define WM831X_UV_LDO4_EINT_WIDTH 1 /* UV_LDO4_EINT */ 3017d4d0a3eSMark Brown #define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */ 3027d4d0a3eSMark Brown #define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */ 3037d4d0a3eSMark Brown #define WM831X_UV_LDO3_EINT_SHIFT 2 /* UV_LDO3_EINT */ 3047d4d0a3eSMark Brown #define WM831X_UV_LDO3_EINT_WIDTH 1 /* UV_LDO3_EINT */ 3057d4d0a3eSMark Brown #define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */ 3067d4d0a3eSMark Brown #define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */ 3077d4d0a3eSMark Brown #define WM831X_UV_LDO2_EINT_SHIFT 1 /* UV_LDO2_EINT */ 3087d4d0a3eSMark Brown #define WM831X_UV_LDO2_EINT_WIDTH 1 /* UV_LDO2_EINT */ 3097d4d0a3eSMark Brown #define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */ 3107d4d0a3eSMark Brown #define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */ 3117d4d0a3eSMark Brown #define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */ 3127d4d0a3eSMark Brown #define WM831X_UV_LDO1_EINT_WIDTH 1 /* UV_LDO1_EINT */ 3137d4d0a3eSMark Brown 3147d4d0a3eSMark Brown /* 3157d4d0a3eSMark Brown * R16404 (0x4014) - Interrupt Status 4 3167d4d0a3eSMark Brown */ 3177d4d0a3eSMark Brown #define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */ 3187d4d0a3eSMark Brown #define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */ 3197d4d0a3eSMark Brown #define WM831X_HC_DC2_EINT_SHIFT 9 /* HC_DC2_EINT */ 3207d4d0a3eSMark Brown #define WM831X_HC_DC2_EINT_WIDTH 1 /* HC_DC2_EINT */ 3217d4d0a3eSMark Brown #define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */ 3227d4d0a3eSMark Brown #define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */ 3237d4d0a3eSMark Brown #define WM831X_HC_DC1_EINT_SHIFT 8 /* HC_DC1_EINT */ 3247d4d0a3eSMark Brown #define WM831X_HC_DC1_EINT_WIDTH 1 /* HC_DC1_EINT */ 3257d4d0a3eSMark Brown #define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */ 3267d4d0a3eSMark Brown #define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */ 3277d4d0a3eSMark Brown #define WM831X_UV_DC4_EINT_SHIFT 3 /* UV_DC4_EINT */ 3287d4d0a3eSMark Brown #define WM831X_UV_DC4_EINT_WIDTH 1 /* UV_DC4_EINT */ 3297d4d0a3eSMark Brown #define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */ 3307d4d0a3eSMark Brown #define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */ 3317d4d0a3eSMark Brown #define WM831X_UV_DC3_EINT_SHIFT 2 /* UV_DC3_EINT */ 3327d4d0a3eSMark Brown #define WM831X_UV_DC3_EINT_WIDTH 1 /* UV_DC3_EINT */ 3337d4d0a3eSMark Brown #define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */ 3347d4d0a3eSMark Brown #define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */ 3357d4d0a3eSMark Brown #define WM831X_UV_DC2_EINT_SHIFT 1 /* UV_DC2_EINT */ 3367d4d0a3eSMark Brown #define WM831X_UV_DC2_EINT_WIDTH 1 /* UV_DC2_EINT */ 3377d4d0a3eSMark Brown #define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */ 3387d4d0a3eSMark Brown #define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */ 3397d4d0a3eSMark Brown #define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */ 3407d4d0a3eSMark Brown #define WM831X_UV_DC1_EINT_WIDTH 1 /* UV_DC1_EINT */ 3417d4d0a3eSMark Brown 3427d4d0a3eSMark Brown /* 3437d4d0a3eSMark Brown * R16405 (0x4015) - Interrupt Status 5 3447d4d0a3eSMark Brown */ 3457d4d0a3eSMark Brown #define WM831X_GP16_EINT 0x8000 /* GP16_EINT */ 3467d4d0a3eSMark Brown #define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */ 3477d4d0a3eSMark Brown #define WM831X_GP16_EINT_SHIFT 15 /* GP16_EINT */ 3487d4d0a3eSMark Brown #define WM831X_GP16_EINT_WIDTH 1 /* GP16_EINT */ 3497d4d0a3eSMark Brown #define WM831X_GP15_EINT 0x4000 /* GP15_EINT */ 3507d4d0a3eSMark Brown #define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */ 3517d4d0a3eSMark Brown #define WM831X_GP15_EINT_SHIFT 14 /* GP15_EINT */ 3527d4d0a3eSMark Brown #define WM831X_GP15_EINT_WIDTH 1 /* GP15_EINT */ 3537d4d0a3eSMark Brown #define WM831X_GP14_EINT 0x2000 /* GP14_EINT */ 3547d4d0a3eSMark Brown #define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */ 3557d4d0a3eSMark Brown #define WM831X_GP14_EINT_SHIFT 13 /* GP14_EINT */ 3567d4d0a3eSMark Brown #define WM831X_GP14_EINT_WIDTH 1 /* GP14_EINT */ 3577d4d0a3eSMark Brown #define WM831X_GP13_EINT 0x1000 /* GP13_EINT */ 3587d4d0a3eSMark Brown #define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */ 3597d4d0a3eSMark Brown #define WM831X_GP13_EINT_SHIFT 12 /* GP13_EINT */ 3607d4d0a3eSMark Brown #define WM831X_GP13_EINT_WIDTH 1 /* GP13_EINT */ 3617d4d0a3eSMark Brown #define WM831X_GP12_EINT 0x0800 /* GP12_EINT */ 3627d4d0a3eSMark Brown #define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */ 3637d4d0a3eSMark Brown #define WM831X_GP12_EINT_SHIFT 11 /* GP12_EINT */ 3647d4d0a3eSMark Brown #define WM831X_GP12_EINT_WIDTH 1 /* GP12_EINT */ 3657d4d0a3eSMark Brown #define WM831X_GP11_EINT 0x0400 /* GP11_EINT */ 3667d4d0a3eSMark Brown #define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */ 3677d4d0a3eSMark Brown #define WM831X_GP11_EINT_SHIFT 10 /* GP11_EINT */ 3687d4d0a3eSMark Brown #define WM831X_GP11_EINT_WIDTH 1 /* GP11_EINT */ 3697d4d0a3eSMark Brown #define WM831X_GP10_EINT 0x0200 /* GP10_EINT */ 3707d4d0a3eSMark Brown #define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */ 3717d4d0a3eSMark Brown #define WM831X_GP10_EINT_SHIFT 9 /* GP10_EINT */ 3727d4d0a3eSMark Brown #define WM831X_GP10_EINT_WIDTH 1 /* GP10_EINT */ 3737d4d0a3eSMark Brown #define WM831X_GP9_EINT 0x0100 /* GP9_EINT */ 3747d4d0a3eSMark Brown #define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */ 3757d4d0a3eSMark Brown #define WM831X_GP9_EINT_SHIFT 8 /* GP9_EINT */ 3767d4d0a3eSMark Brown #define WM831X_GP9_EINT_WIDTH 1 /* GP9_EINT */ 3777d4d0a3eSMark Brown #define WM831X_GP8_EINT 0x0080 /* GP8_EINT */ 3787d4d0a3eSMark Brown #define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */ 3797d4d0a3eSMark Brown #define WM831X_GP8_EINT_SHIFT 7 /* GP8_EINT */ 3807d4d0a3eSMark Brown #define WM831X_GP8_EINT_WIDTH 1 /* GP8_EINT */ 3817d4d0a3eSMark Brown #define WM831X_GP7_EINT 0x0040 /* GP7_EINT */ 3827d4d0a3eSMark Brown #define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */ 3837d4d0a3eSMark Brown #define WM831X_GP7_EINT_SHIFT 6 /* GP7_EINT */ 3847d4d0a3eSMark Brown #define WM831X_GP7_EINT_WIDTH 1 /* GP7_EINT */ 3857d4d0a3eSMark Brown #define WM831X_GP6_EINT 0x0020 /* GP6_EINT */ 3867d4d0a3eSMark Brown #define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 3877d4d0a3eSMark Brown #define WM831X_GP6_EINT_SHIFT 5 /* GP6_EINT */ 3887d4d0a3eSMark Brown #define WM831X_GP6_EINT_WIDTH 1 /* GP6_EINT */ 3897d4d0a3eSMark Brown #define WM831X_GP5_EINT 0x0010 /* GP5_EINT */ 3907d4d0a3eSMark Brown #define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3917d4d0a3eSMark Brown #define WM831X_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3927d4d0a3eSMark Brown #define WM831X_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3937d4d0a3eSMark Brown #define WM831X_GP4_EINT 0x0008 /* GP4_EINT */ 3947d4d0a3eSMark Brown #define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3957d4d0a3eSMark Brown #define WM831X_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3967d4d0a3eSMark Brown #define WM831X_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3977d4d0a3eSMark Brown #define WM831X_GP3_EINT 0x0004 /* GP3_EINT */ 3987d4d0a3eSMark Brown #define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3997d4d0a3eSMark Brown #define WM831X_GP3_EINT_SHIFT 2 /* GP3_EINT */ 4007d4d0a3eSMark Brown #define WM831X_GP3_EINT_WIDTH 1 /* GP3_EINT */ 4017d4d0a3eSMark Brown #define WM831X_GP2_EINT 0x0002 /* GP2_EINT */ 4027d4d0a3eSMark Brown #define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 4037d4d0a3eSMark Brown #define WM831X_GP2_EINT_SHIFT 1 /* GP2_EINT */ 4047d4d0a3eSMark Brown #define WM831X_GP2_EINT_WIDTH 1 /* GP2_EINT */ 4057d4d0a3eSMark Brown #define WM831X_GP1_EINT 0x0001 /* GP1_EINT */ 4067d4d0a3eSMark Brown #define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 4077d4d0a3eSMark Brown #define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */ 4087d4d0a3eSMark Brown #define WM831X_GP1_EINT_WIDTH 1 /* GP1_EINT */ 4097d4d0a3eSMark Brown 4107d4d0a3eSMark Brown /* 4117d4d0a3eSMark Brown * R16407 (0x4017) - IRQ Config 4127d4d0a3eSMark Brown */ 4137d4d0a3eSMark Brown #define WM831X_IRQ_OD 0x0002 /* IRQ_OD */ 4147d4d0a3eSMark Brown #define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */ 4157d4d0a3eSMark Brown #define WM831X_IRQ_OD_SHIFT 1 /* IRQ_OD */ 4167d4d0a3eSMark Brown #define WM831X_IRQ_OD_WIDTH 1 /* IRQ_OD */ 4177d4d0a3eSMark Brown #define WM831X_IM_IRQ 0x0001 /* IM_IRQ */ 4187d4d0a3eSMark Brown #define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 4197d4d0a3eSMark Brown #define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */ 4207d4d0a3eSMark Brown #define WM831X_IM_IRQ_WIDTH 1 /* IM_IRQ */ 4217d4d0a3eSMark Brown 4227d4d0a3eSMark Brown /* 4237d4d0a3eSMark Brown * R16408 (0x4018) - System Interrupts Mask 4247d4d0a3eSMark Brown */ 4257d4d0a3eSMark Brown #define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */ 4267d4d0a3eSMark Brown #define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */ 4277d4d0a3eSMark Brown #define WM831X_IM_PS_INT_SHIFT 15 /* IM_PS_INT */ 4287d4d0a3eSMark Brown #define WM831X_IM_PS_INT_WIDTH 1 /* IM_PS_INT */ 4297d4d0a3eSMark Brown #define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */ 4307d4d0a3eSMark Brown #define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */ 4317d4d0a3eSMark Brown #define WM831X_IM_TEMP_INT_SHIFT 14 /* IM_TEMP_INT */ 4327d4d0a3eSMark Brown #define WM831X_IM_TEMP_INT_WIDTH 1 /* IM_TEMP_INT */ 4337d4d0a3eSMark Brown #define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */ 4347d4d0a3eSMark Brown #define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */ 4357d4d0a3eSMark Brown #define WM831X_IM_GP_INT_SHIFT 13 /* IM_GP_INT */ 4367d4d0a3eSMark Brown #define WM831X_IM_GP_INT_WIDTH 1 /* IM_GP_INT */ 4377d4d0a3eSMark Brown #define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */ 4387d4d0a3eSMark Brown #define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */ 4397d4d0a3eSMark Brown #define WM831X_IM_ON_PIN_INT_SHIFT 12 /* IM_ON_PIN_INT */ 4407d4d0a3eSMark Brown #define WM831X_IM_ON_PIN_INT_WIDTH 1 /* IM_ON_PIN_INT */ 4417d4d0a3eSMark Brown #define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */ 4427d4d0a3eSMark Brown #define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */ 4437d4d0a3eSMark Brown #define WM831X_IM_WDOG_INT_SHIFT 11 /* IM_WDOG_INT */ 4447d4d0a3eSMark Brown #define WM831X_IM_WDOG_INT_WIDTH 1 /* IM_WDOG_INT */ 4457d4d0a3eSMark Brown #define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */ 4467d4d0a3eSMark Brown #define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */ 4477d4d0a3eSMark Brown #define WM831X_IM_TCHDATA_INT_SHIFT 10 /* IM_TCHDATA_INT */ 4487d4d0a3eSMark Brown #define WM831X_IM_TCHDATA_INT_WIDTH 1 /* IM_TCHDATA_INT */ 4497d4d0a3eSMark Brown #define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */ 4507d4d0a3eSMark Brown #define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */ 4517d4d0a3eSMark Brown #define WM831X_IM_TCHPD_INT_SHIFT 9 /* IM_TCHPD_INT */ 4527d4d0a3eSMark Brown #define WM831X_IM_TCHPD_INT_WIDTH 1 /* IM_TCHPD_INT */ 4537d4d0a3eSMark Brown #define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */ 4547d4d0a3eSMark Brown #define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */ 4557d4d0a3eSMark Brown #define WM831X_IM_AUXADC_INT_SHIFT 8 /* IM_AUXADC_INT */ 4567d4d0a3eSMark Brown #define WM831X_IM_AUXADC_INT_WIDTH 1 /* IM_AUXADC_INT */ 4577d4d0a3eSMark Brown #define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */ 4587d4d0a3eSMark Brown #define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */ 4597d4d0a3eSMark Brown #define WM831X_IM_PPM_INT_SHIFT 7 /* IM_PPM_INT */ 4607d4d0a3eSMark Brown #define WM831X_IM_PPM_INT_WIDTH 1 /* IM_PPM_INT */ 4617d4d0a3eSMark Brown #define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */ 4627d4d0a3eSMark Brown #define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */ 4637d4d0a3eSMark Brown #define WM831X_IM_CS_INT_SHIFT 6 /* IM_CS_INT */ 4647d4d0a3eSMark Brown #define WM831X_IM_CS_INT_WIDTH 1 /* IM_CS_INT */ 4657d4d0a3eSMark Brown #define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */ 4667d4d0a3eSMark Brown #define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */ 4677d4d0a3eSMark Brown #define WM831X_IM_RTC_INT_SHIFT 5 /* IM_RTC_INT */ 4687d4d0a3eSMark Brown #define WM831X_IM_RTC_INT_WIDTH 1 /* IM_RTC_INT */ 4697d4d0a3eSMark Brown #define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */ 4707d4d0a3eSMark Brown #define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */ 4717d4d0a3eSMark Brown #define WM831X_IM_OTP_INT_SHIFT 4 /* IM_OTP_INT */ 4727d4d0a3eSMark Brown #define WM831X_IM_OTP_INT_WIDTH 1 /* IM_OTP_INT */ 4737d4d0a3eSMark Brown #define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */ 4747d4d0a3eSMark Brown #define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */ 4757d4d0a3eSMark Brown #define WM831X_IM_CHILD_INT_SHIFT 3 /* IM_CHILD_INT */ 4767d4d0a3eSMark Brown #define WM831X_IM_CHILD_INT_WIDTH 1 /* IM_CHILD_INT */ 4777d4d0a3eSMark Brown #define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */ 4787d4d0a3eSMark Brown #define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */ 4797d4d0a3eSMark Brown #define WM831X_IM_CHG_INT_SHIFT 2 /* IM_CHG_INT */ 4807d4d0a3eSMark Brown #define WM831X_IM_CHG_INT_WIDTH 1 /* IM_CHG_INT */ 4817d4d0a3eSMark Brown #define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */ 4827d4d0a3eSMark Brown #define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */ 4837d4d0a3eSMark Brown #define WM831X_IM_HC_INT_SHIFT 1 /* IM_HC_INT */ 4847d4d0a3eSMark Brown #define WM831X_IM_HC_INT_WIDTH 1 /* IM_HC_INT */ 4857d4d0a3eSMark Brown #define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */ 4867d4d0a3eSMark Brown #define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */ 4877d4d0a3eSMark Brown #define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */ 4887d4d0a3eSMark Brown #define WM831X_IM_UV_INT_WIDTH 1 /* IM_UV_INT */ 4897d4d0a3eSMark Brown 4907d4d0a3eSMark Brown /* 4917d4d0a3eSMark Brown * R16409 (0x4019) - Interrupt Status 1 Mask 4927d4d0a3eSMark Brown */ 4937d4d0a3eSMark Brown #define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */ 4947d4d0a3eSMark Brown #define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */ 4957d4d0a3eSMark Brown #define WM831X_IM_PPM_SYSLO_EINT_SHIFT 15 /* IM_PPM_SYSLO_EINT */ 4967d4d0a3eSMark Brown #define WM831X_IM_PPM_SYSLO_EINT_WIDTH 1 /* IM_PPM_SYSLO_EINT */ 4977d4d0a3eSMark Brown #define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */ 4987d4d0a3eSMark Brown #define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */ 4997d4d0a3eSMark Brown #define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT 14 /* IM_PPM_PWR_SRC_EINT */ 5007d4d0a3eSMark Brown #define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH 1 /* IM_PPM_PWR_SRC_EINT */ 5017d4d0a3eSMark Brown #define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */ 5027d4d0a3eSMark Brown #define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */ 5037d4d0a3eSMark Brown #define WM831X_IM_PPM_USB_CURR_EINT_SHIFT 13 /* IM_PPM_USB_CURR_EINT */ 5047d4d0a3eSMark Brown #define WM831X_IM_PPM_USB_CURR_EINT_WIDTH 1 /* IM_PPM_USB_CURR_EINT */ 5057d4d0a3eSMark Brown #define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */ 5067d4d0a3eSMark Brown #define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */ 5077d4d0a3eSMark Brown #define WM831X_IM_ON_PIN_EINT_SHIFT 12 /* IM_ON_PIN_EINT */ 5087d4d0a3eSMark Brown #define WM831X_IM_ON_PIN_EINT_WIDTH 1 /* IM_ON_PIN_EINT */ 5097d4d0a3eSMark Brown #define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */ 5107d4d0a3eSMark Brown #define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */ 5117d4d0a3eSMark Brown #define WM831X_IM_WDOG_TO_EINT_SHIFT 11 /* IM_WDOG_TO_EINT */ 5127d4d0a3eSMark Brown #define WM831X_IM_WDOG_TO_EINT_WIDTH 1 /* IM_WDOG_TO_EINT */ 5137d4d0a3eSMark Brown #define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */ 5147d4d0a3eSMark Brown #define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */ 5157d4d0a3eSMark Brown #define WM831X_IM_TCHDATA_EINT_SHIFT 10 /* IM_TCHDATA_EINT */ 5167d4d0a3eSMark Brown #define WM831X_IM_TCHDATA_EINT_WIDTH 1 /* IM_TCHDATA_EINT */ 5177d4d0a3eSMark Brown #define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */ 5187d4d0a3eSMark Brown #define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */ 5197d4d0a3eSMark Brown #define WM831X_IM_TCHPD_EINT_SHIFT 9 /* IM_TCHPD_EINT */ 5207d4d0a3eSMark Brown #define WM831X_IM_TCHPD_EINT_WIDTH 1 /* IM_TCHPD_EINT */ 5217d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */ 5227d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */ 5237d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DATA_EINT_SHIFT 8 /* IM_AUXADC_DATA_EINT */ 5247d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DATA_EINT_WIDTH 1 /* IM_AUXADC_DATA_EINT */ 5257d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */ 5267d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */ 5277d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT 7 /* IM_AUXADC_DCOMP4_EINT */ 5287d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH 1 /* IM_AUXADC_DCOMP4_EINT */ 5297d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */ 5307d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */ 5317d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT 6 /* IM_AUXADC_DCOMP3_EINT */ 5327d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH 1 /* IM_AUXADC_DCOMP3_EINT */ 5337d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */ 5347d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */ 5357d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT 5 /* IM_AUXADC_DCOMP2_EINT */ 5367d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH 1 /* IM_AUXADC_DCOMP2_EINT */ 5377d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */ 5387d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */ 5397d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT 4 /* IM_AUXADC_DCOMP1_EINT */ 5407d4d0a3eSMark Brown #define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH 1 /* IM_AUXADC_DCOMP1_EINT */ 5417d4d0a3eSMark Brown #define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */ 5427d4d0a3eSMark Brown #define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */ 5437d4d0a3eSMark Brown #define WM831X_IM_RTC_PER_EINT_SHIFT 3 /* IM_RTC_PER_EINT */ 5447d4d0a3eSMark Brown #define WM831X_IM_RTC_PER_EINT_WIDTH 1 /* IM_RTC_PER_EINT */ 5457d4d0a3eSMark Brown #define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */ 5467d4d0a3eSMark Brown #define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */ 5477d4d0a3eSMark Brown #define WM831X_IM_RTC_ALM_EINT_SHIFT 2 /* IM_RTC_ALM_EINT */ 5487d4d0a3eSMark Brown #define WM831X_IM_RTC_ALM_EINT_WIDTH 1 /* IM_RTC_ALM_EINT */ 5497d4d0a3eSMark Brown #define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */ 5507d4d0a3eSMark Brown #define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */ 5517d4d0a3eSMark Brown #define WM831X_IM_TEMP_THW_EINT_SHIFT 1 /* IM_TEMP_THW_EINT */ 5527d4d0a3eSMark Brown #define WM831X_IM_TEMP_THW_EINT_WIDTH 1 /* IM_TEMP_THW_EINT */ 5537d4d0a3eSMark Brown 5547d4d0a3eSMark Brown /* 5557d4d0a3eSMark Brown * R16410 (0x401A) - Interrupt Status 2 Mask 5567d4d0a3eSMark Brown */ 5577d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */ 5587d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */ 5597d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT 15 /* IM_CHG_BATT_HOT_EINT */ 5607d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH 1 /* IM_CHG_BATT_HOT_EINT */ 5617d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */ 5627d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */ 5637d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT 14 /* IM_CHG_BATT_COLD_EINT */ 5647d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH 1 /* IM_CHG_BATT_COLD_EINT */ 5657d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */ 5667d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */ 5677d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT 13 /* IM_CHG_BATT_FAIL_EINT */ 5687d4d0a3eSMark Brown #define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH 1 /* IM_CHG_BATT_FAIL_EINT */ 5697d4d0a3eSMark Brown #define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */ 5707d4d0a3eSMark Brown #define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */ 5717d4d0a3eSMark Brown #define WM831X_IM_CHG_OV_EINT_SHIFT 12 /* IM_CHG_OV_EINT */ 5727d4d0a3eSMark Brown #define WM831X_IM_CHG_OV_EINT_WIDTH 1 /* IM_CHG_OV_EINT */ 5737d4d0a3eSMark Brown #define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */ 5747d4d0a3eSMark Brown #define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */ 5757d4d0a3eSMark Brown #define WM831X_IM_CHG_END_EINT_SHIFT 11 /* IM_CHG_END_EINT */ 5767d4d0a3eSMark Brown #define WM831X_IM_CHG_END_EINT_WIDTH 1 /* IM_CHG_END_EINT */ 5777d4d0a3eSMark Brown #define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */ 5787d4d0a3eSMark Brown #define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */ 5797d4d0a3eSMark Brown #define WM831X_IM_CHG_TO_EINT_SHIFT 10 /* IM_CHG_TO_EINT */ 5807d4d0a3eSMark Brown #define WM831X_IM_CHG_TO_EINT_WIDTH 1 /* IM_CHG_TO_EINT */ 5817d4d0a3eSMark Brown #define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */ 5827d4d0a3eSMark Brown #define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */ 5837d4d0a3eSMark Brown #define WM831X_IM_CHG_MODE_EINT_SHIFT 9 /* IM_CHG_MODE_EINT */ 5847d4d0a3eSMark Brown #define WM831X_IM_CHG_MODE_EINT_WIDTH 1 /* IM_CHG_MODE_EINT */ 5857d4d0a3eSMark Brown #define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */ 5867d4d0a3eSMark Brown #define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */ 5877d4d0a3eSMark Brown #define WM831X_IM_CHG_START_EINT_SHIFT 8 /* IM_CHG_START_EINT */ 5887d4d0a3eSMark Brown #define WM831X_IM_CHG_START_EINT_WIDTH 1 /* IM_CHG_START_EINT */ 5897d4d0a3eSMark Brown #define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */ 5907d4d0a3eSMark Brown #define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */ 5917d4d0a3eSMark Brown #define WM831X_IM_CS2_EINT_SHIFT 7 /* IM_CS2_EINT */ 5927d4d0a3eSMark Brown #define WM831X_IM_CS2_EINT_WIDTH 1 /* IM_CS2_EINT */ 5937d4d0a3eSMark Brown #define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */ 5947d4d0a3eSMark Brown #define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */ 5957d4d0a3eSMark Brown #define WM831X_IM_CS1_EINT_SHIFT 6 /* IM_CS1_EINT */ 5967d4d0a3eSMark Brown #define WM831X_IM_CS1_EINT_WIDTH 1 /* IM_CS1_EINT */ 5977d4d0a3eSMark Brown #define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */ 5987d4d0a3eSMark Brown #define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */ 5997d4d0a3eSMark Brown #define WM831X_IM_OTP_CMD_END_EINT_SHIFT 5 /* IM_OTP_CMD_END_EINT */ 6007d4d0a3eSMark Brown #define WM831X_IM_OTP_CMD_END_EINT_WIDTH 1 /* IM_OTP_CMD_END_EINT */ 6017d4d0a3eSMark Brown #define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */ 6027d4d0a3eSMark Brown #define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */ 6037d4d0a3eSMark Brown #define WM831X_IM_OTP_ERR_EINT_SHIFT 4 /* IM_OTP_ERR_EINT */ 6047d4d0a3eSMark Brown #define WM831X_IM_OTP_ERR_EINT_WIDTH 1 /* IM_OTP_ERR_EINT */ 6057d4d0a3eSMark Brown #define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */ 6067d4d0a3eSMark Brown #define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */ 6077d4d0a3eSMark Brown #define WM831X_IM_PS_POR_EINT_SHIFT 2 /* IM_PS_POR_EINT */ 6087d4d0a3eSMark Brown #define WM831X_IM_PS_POR_EINT_WIDTH 1 /* IM_PS_POR_EINT */ 6097d4d0a3eSMark Brown #define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */ 6107d4d0a3eSMark Brown #define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */ 6117d4d0a3eSMark Brown #define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT 1 /* IM_PS_SLEEP_OFF_EINT */ 6127d4d0a3eSMark Brown #define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH 1 /* IM_PS_SLEEP_OFF_EINT */ 6137d4d0a3eSMark Brown #define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */ 6147d4d0a3eSMark Brown #define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */ 6157d4d0a3eSMark Brown #define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */ 6167d4d0a3eSMark Brown #define WM831X_IM_PS_ON_WAKE_EINT_WIDTH 1 /* IM_PS_ON_WAKE_EINT */ 6177d4d0a3eSMark Brown 6187d4d0a3eSMark Brown /* 6197d4d0a3eSMark Brown * R16411 (0x401B) - Interrupt Status 3 Mask 6207d4d0a3eSMark Brown */ 6217d4d0a3eSMark Brown #define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */ 6227d4d0a3eSMark Brown #define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */ 6237d4d0a3eSMark Brown #define WM831X_IM_UV_LDO10_EINT_SHIFT 9 /* IM_UV_LDO10_EINT */ 6247d4d0a3eSMark Brown #define WM831X_IM_UV_LDO10_EINT_WIDTH 1 /* IM_UV_LDO10_EINT */ 6257d4d0a3eSMark Brown #define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */ 6267d4d0a3eSMark Brown #define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */ 6277d4d0a3eSMark Brown #define WM831X_IM_UV_LDO9_EINT_SHIFT 8 /* IM_UV_LDO9_EINT */ 6287d4d0a3eSMark Brown #define WM831X_IM_UV_LDO9_EINT_WIDTH 1 /* IM_UV_LDO9_EINT */ 6297d4d0a3eSMark Brown #define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */ 6307d4d0a3eSMark Brown #define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */ 6317d4d0a3eSMark Brown #define WM831X_IM_UV_LDO8_EINT_SHIFT 7 /* IM_UV_LDO8_EINT */ 6327d4d0a3eSMark Brown #define WM831X_IM_UV_LDO8_EINT_WIDTH 1 /* IM_UV_LDO8_EINT */ 6337d4d0a3eSMark Brown #define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */ 6347d4d0a3eSMark Brown #define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */ 6357d4d0a3eSMark Brown #define WM831X_IM_UV_LDO7_EINT_SHIFT 6 /* IM_UV_LDO7_EINT */ 6367d4d0a3eSMark Brown #define WM831X_IM_UV_LDO7_EINT_WIDTH 1 /* IM_UV_LDO7_EINT */ 6377d4d0a3eSMark Brown #define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */ 6387d4d0a3eSMark Brown #define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */ 6397d4d0a3eSMark Brown #define WM831X_IM_UV_LDO6_EINT_SHIFT 5 /* IM_UV_LDO6_EINT */ 6407d4d0a3eSMark Brown #define WM831X_IM_UV_LDO6_EINT_WIDTH 1 /* IM_UV_LDO6_EINT */ 6417d4d0a3eSMark Brown #define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */ 6427d4d0a3eSMark Brown #define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */ 6437d4d0a3eSMark Brown #define WM831X_IM_UV_LDO5_EINT_SHIFT 4 /* IM_UV_LDO5_EINT */ 6447d4d0a3eSMark Brown #define WM831X_IM_UV_LDO5_EINT_WIDTH 1 /* IM_UV_LDO5_EINT */ 6457d4d0a3eSMark Brown #define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */ 6467d4d0a3eSMark Brown #define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */ 6477d4d0a3eSMark Brown #define WM831X_IM_UV_LDO4_EINT_SHIFT 3 /* IM_UV_LDO4_EINT */ 6487d4d0a3eSMark Brown #define WM831X_IM_UV_LDO4_EINT_WIDTH 1 /* IM_UV_LDO4_EINT */ 6497d4d0a3eSMark Brown #define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */ 6507d4d0a3eSMark Brown #define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */ 6517d4d0a3eSMark Brown #define WM831X_IM_UV_LDO3_EINT_SHIFT 2 /* IM_UV_LDO3_EINT */ 6527d4d0a3eSMark Brown #define WM831X_IM_UV_LDO3_EINT_WIDTH 1 /* IM_UV_LDO3_EINT */ 6537d4d0a3eSMark Brown #define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */ 6547d4d0a3eSMark Brown #define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */ 6557d4d0a3eSMark Brown #define WM831X_IM_UV_LDO2_EINT_SHIFT 1 /* IM_UV_LDO2_EINT */ 6567d4d0a3eSMark Brown #define WM831X_IM_UV_LDO2_EINT_WIDTH 1 /* IM_UV_LDO2_EINT */ 6577d4d0a3eSMark Brown #define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */ 6587d4d0a3eSMark Brown #define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */ 6597d4d0a3eSMark Brown #define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */ 6607d4d0a3eSMark Brown #define WM831X_IM_UV_LDO1_EINT_WIDTH 1 /* IM_UV_LDO1_EINT */ 6617d4d0a3eSMark Brown 6627d4d0a3eSMark Brown /* 6637d4d0a3eSMark Brown * R16412 (0x401C) - Interrupt Status 4 Mask 6647d4d0a3eSMark Brown */ 6657d4d0a3eSMark Brown #define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */ 6667d4d0a3eSMark Brown #define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */ 6677d4d0a3eSMark Brown #define WM831X_IM_HC_DC2_EINT_SHIFT 9 /* IM_HC_DC2_EINT */ 6687d4d0a3eSMark Brown #define WM831X_IM_HC_DC2_EINT_WIDTH 1 /* IM_HC_DC2_EINT */ 6697d4d0a3eSMark Brown #define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */ 6707d4d0a3eSMark Brown #define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */ 6717d4d0a3eSMark Brown #define WM831X_IM_HC_DC1_EINT_SHIFT 8 /* IM_HC_DC1_EINT */ 6727d4d0a3eSMark Brown #define WM831X_IM_HC_DC1_EINT_WIDTH 1 /* IM_HC_DC1_EINT */ 6737d4d0a3eSMark Brown #define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */ 6747d4d0a3eSMark Brown #define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */ 6757d4d0a3eSMark Brown #define WM831X_IM_UV_DC4_EINT_SHIFT 3 /* IM_UV_DC4_EINT */ 6767d4d0a3eSMark Brown #define WM831X_IM_UV_DC4_EINT_WIDTH 1 /* IM_UV_DC4_EINT */ 6777d4d0a3eSMark Brown #define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */ 6787d4d0a3eSMark Brown #define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */ 6797d4d0a3eSMark Brown #define WM831X_IM_UV_DC3_EINT_SHIFT 2 /* IM_UV_DC3_EINT */ 6807d4d0a3eSMark Brown #define WM831X_IM_UV_DC3_EINT_WIDTH 1 /* IM_UV_DC3_EINT */ 6817d4d0a3eSMark Brown #define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */ 6827d4d0a3eSMark Brown #define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */ 6837d4d0a3eSMark Brown #define WM831X_IM_UV_DC2_EINT_SHIFT 1 /* IM_UV_DC2_EINT */ 6847d4d0a3eSMark Brown #define WM831X_IM_UV_DC2_EINT_WIDTH 1 /* IM_UV_DC2_EINT */ 6857d4d0a3eSMark Brown #define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */ 6867d4d0a3eSMark Brown #define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */ 6877d4d0a3eSMark Brown #define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */ 6887d4d0a3eSMark Brown #define WM831X_IM_UV_DC1_EINT_WIDTH 1 /* IM_UV_DC1_EINT */ 6897d4d0a3eSMark Brown 6907d4d0a3eSMark Brown /* 6917d4d0a3eSMark Brown * R16413 (0x401D) - Interrupt Status 5 Mask 6927d4d0a3eSMark Brown */ 6937d4d0a3eSMark Brown #define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */ 6947d4d0a3eSMark Brown #define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */ 6957d4d0a3eSMark Brown #define WM831X_IM_GP16_EINT_SHIFT 15 /* IM_GP16_EINT */ 6967d4d0a3eSMark Brown #define WM831X_IM_GP16_EINT_WIDTH 1 /* IM_GP16_EINT */ 6977d4d0a3eSMark Brown #define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */ 6987d4d0a3eSMark Brown #define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */ 6997d4d0a3eSMark Brown #define WM831X_IM_GP15_EINT_SHIFT 14 /* IM_GP15_EINT */ 7007d4d0a3eSMark Brown #define WM831X_IM_GP15_EINT_WIDTH 1 /* IM_GP15_EINT */ 7017d4d0a3eSMark Brown #define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */ 7027d4d0a3eSMark Brown #define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */ 7037d4d0a3eSMark Brown #define WM831X_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */ 7047d4d0a3eSMark Brown #define WM831X_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */ 7057d4d0a3eSMark Brown #define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */ 7067d4d0a3eSMark Brown #define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */ 7077d4d0a3eSMark Brown #define WM831X_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */ 7087d4d0a3eSMark Brown #define WM831X_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */ 7097d4d0a3eSMark Brown #define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */ 7107d4d0a3eSMark Brown #define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */ 7117d4d0a3eSMark Brown #define WM831X_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */ 7127d4d0a3eSMark Brown #define WM831X_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */ 7137d4d0a3eSMark Brown #define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ 7147d4d0a3eSMark Brown #define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ 7157d4d0a3eSMark Brown #define WM831X_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ 7167d4d0a3eSMark Brown #define WM831X_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ 7177d4d0a3eSMark Brown #define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ 7187d4d0a3eSMark Brown #define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ 7197d4d0a3eSMark Brown #define WM831X_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ 7207d4d0a3eSMark Brown #define WM831X_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ 7217d4d0a3eSMark Brown #define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ 7227d4d0a3eSMark Brown #define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ 7237d4d0a3eSMark Brown #define WM831X_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ 7247d4d0a3eSMark Brown #define WM831X_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ 7257d4d0a3eSMark Brown #define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ 7267d4d0a3eSMark Brown #define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ 7277d4d0a3eSMark Brown #define WM831X_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ 7287d4d0a3eSMark Brown #define WM831X_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ 7297d4d0a3eSMark Brown #define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ 7307d4d0a3eSMark Brown #define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ 7317d4d0a3eSMark Brown #define WM831X_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ 7327d4d0a3eSMark Brown #define WM831X_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ 7337d4d0a3eSMark Brown #define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 7347d4d0a3eSMark Brown #define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 7357d4d0a3eSMark Brown #define WM831X_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 7367d4d0a3eSMark Brown #define WM831X_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 7377d4d0a3eSMark Brown #define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 7387d4d0a3eSMark Brown #define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 7397d4d0a3eSMark Brown #define WM831X_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 7407d4d0a3eSMark Brown #define WM831X_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 7417d4d0a3eSMark Brown #define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 7427d4d0a3eSMark Brown #define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 7437d4d0a3eSMark Brown #define WM831X_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 7447d4d0a3eSMark Brown #define WM831X_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 7457d4d0a3eSMark Brown #define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 7467d4d0a3eSMark Brown #define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 7477d4d0a3eSMark Brown #define WM831X_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 7487d4d0a3eSMark Brown #define WM831X_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 7497d4d0a3eSMark Brown #define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 7507d4d0a3eSMark Brown #define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 7517d4d0a3eSMark Brown #define WM831X_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 7527d4d0a3eSMark Brown #define WM831X_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 7537d4d0a3eSMark Brown #define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 7547d4d0a3eSMark Brown #define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 7557d4d0a3eSMark Brown #define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 7567d4d0a3eSMark Brown #define WM831X_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 7577d4d0a3eSMark Brown 7587d4d0a3eSMark Brown 7597d4d0a3eSMark Brown #endif 760