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/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dflexcan.h15 u8 tmstamp; /* 0x00 Timestamp */
16 u8 ctrl; /* 0x01 Control */
17 u16 idh; /* 0x02 ID High */
18 u16 idl; /* 0x04 ID High */
19 u8 data[8]; /* 0x06 8 Byte Data Field */
20 u16 res; /* 0x0E */
22 u16 ctrl; /* 0x00 Control/Status */
23 u16 tmstamp; /* 0x02 Timestamp */
24 u32 id; /* 0x04 Identifier */
25 u8 data[8]; /* 0x08 8 Byte Data Field */
[all …]
/openbmc/linux/drivers/atm/
H A Dmidway.h19 #define MAP_MAX_SIZE 0x00400000 /* memory window for max config */
20 #define EPROM_SIZE 0x00010000
21 #define MEM_VALID 0xffc00000 /* mask base address with this */
22 #define PHY_BASE 0x00020000 /* offset of PHY register are */
23 #define REG_BASE 0x00040000 /* offset of Midway register area */
24 #define RAM_BASE 0x00200000 /* offset of RAM area */
25 #define RAM_INCREMENT 0x00020000 /* probe for RAM every 128kB */
50 #define MID_RES_ID_MCON 0x00 /* Midway Reset/ID */
52 #define MID_ID 0xf0000000 /* Midway version */
54 #define MID_MOTHER_ID 0x00000700 /* mother board id */
[all …]
/openbmc/linux/drivers/video/fbdev/vermilion/
H A Dvermilion.h23 #define VML_DEVICE_GPU 0x5002
24 #define VML_DEVICE_VDC 0x5009
37 #define VML_R_MASK 0x3FF00000
39 #define VML_G_MASK 0x000FFC00
41 #define VML_B_MASK 0x000003FF
42 #define VML_B_SHIFT 0
45 #define VML_DSPCCNTR 0x00072180
46 #define VML_GFX_ENABLE 0x80000000
47 #define VML_GFX_GAMMABYPASS 0x40000000
48 #define VML_GFX_ARGB1555 0x0C000000
[all …]
/openbmc/linux/drivers/net/usb/
H A Dsmsc95xx.h12 #define TX_CMD_A_DATA_OFFSET_ (0x001F0000) /* Data Start Offset */
13 #define TX_CMD_A_FIRST_SEG_ (0x00002000) /* First Segment */
14 #define TX_CMD_A_LAST_SEG_ (0x00001000) /* Last Segment */
15 #define TX_CMD_A_BUF_SIZE_ (0x000007FF) /* Buffer Size */
17 #define TX_CMD_B_CSUM_ENABLE (0x00004000) /* TX Checksum Enable */
18 #define TX_CMD_B_ADD_CRC_DIS_ (0x00002000) /* Add CRC Disable */
19 #define TX_CMD_B_DIS_PADDING_ (0x00001000) /* Disable Frame Padding */
20 #define TX_CMD_B_FRAME_LENGTH_ (0x000007FF) /* Frame Length (bytes) */
23 #define RX_STS_FF_ (0x40000000) /* Filter Fail */
24 #define RX_STS_FL_ (0x3FFF0000) /* Frame Length */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dtonga_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
H A Diceland_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
41 #define SDMA_SUBOP_TIMESTAMP_SET 0
44 #define SDMA_SUBOP_COPY_LINEAR 0
50 #define SDMA_SUBOP_WRITE_LINEAR 0
54 #define SDMA_PKT_HEADER_op_offset 0
55 #define SDMA_PKT_HEADER_op_mask 0x000000FF
56 #define SDMA_PKT_HEADER_op_shift 0
60 #define SDMA_PKT_HEADER_sub_op_offset 0
61 #define SDMA_PKT_HEADER_sub_op_mask 0x000000FF
71 #define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0
[all …]
H A Dvega10_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
42 #define SDMA_SUBOP_TIMESTAMP_SET 0
45 #define SDMA_SUBOP_COPY_LINEAR 0
53 #define SDMA_SUBOP_WRITE_LINEAR 0
55 #define SDMA_SUBOP_PTEPDE_GEN 0
65 #define SDMA_OP_AQL_COPY 0
66 #define SDMA_OP_AQL_BARRIER_OR 0
69 #define SDMA_PKT_HEADER_op_offset 0
70 #define SDMA_PKT_HEADER_op_mask 0x000000FF
71 #define SDMA_PKT_HEADER_op_shift 0
[all …]
H A Dnavi10_sdma_pkt_open.h26 #define SDMA_OP_NOP 0
44 #define SDMA_SUBOP_TIMESTAMP_SET 0
47 #define SDMA_SUBOP_COPY_LINEAR 0
60 #define SDMA_SUBOP_WRITE_LINEAR 0
63 #define SDMA_SUBOP_PTEPDE_GEN 0
73 #define SDMA_OP_AQL_COPY 0
74 #define SDMA_OP_AQL_BARRIER_OR 0
77 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16)
81 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11)
89 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2)
[all …]
/openbmc/linux/drivers/staging/emxx_udc/
H A Demxx_udc.h21 #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */
22 #define INT_VBUS 0 /* IRQ for GPIO_P153 */
46 #define U2F_DISABLE 0
60 #define MAX_TEST_MODE_NUM 0x05
63 /*------- (0x0004) USB Status Register */
73 /*------- (0x0008) USB Address Register */
74 #define USB_ADDR 0x007F0000
77 #define FRAME 0x000007FF
81 /*------- (0x000C) UTMI Characteristic 1 Register */
86 /*------- (0x0010) TEST Control Register */
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspr600_mt47h128m8_3_266_cl5_async.c12 0x00000001,
13 0x00000000,
14 0x01000000,
15 0x00000101,
16 0x00000001,
17 0x01000000,
18 0x00010001,
19 0x00000100,
20 0x00010001,
21 0x00000003,
[all …]
/openbmc/qemu/hw/pci-host/
H A Dgt64120.c42 #define GT_REGS (0x1000 >> 2)
45 #define GT_CPU (0x000 >> 2)
46 #define GT_MULTI (0x120 >> 2)
48 REG32(GT_CPU, 0x000)
52 #define GT_SCS10LD (0x008 >> 2)
53 #define GT_SCS10HD (0x010 >> 2)
54 #define GT_SCS32LD (0x018 >> 2)
55 #define GT_SCS32HD (0x020 >> 2)
56 #define GT_CS20LD (0x028 >> 2)
57 #define GT_CS20HD (0x030 >> 2)
[all …]
/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_display_regs.h6 #define MCDE_IMSCPP 0x00000104
7 #define MCDE_RISPP 0x00000114
8 #define MCDE_MISPP 0x00000124
9 #define MCDE_SISPP 0x00000134
11 #define MCDE_PP_VCMPA BIT(0)
21 #define MCDE_IMSCOVL 0x00000108
22 #define MCDE_RISOVL 0x00000118
23 #define MCDE_MISOVL 0x00000128
24 #define MCDE_SISOVL 0x00000138
27 #define MCDE_IMSCCHNL 0x0000010C
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h12 #define TV_CTL _MMIO(0x68000)
20 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
31 # define TV_OVERSAMPLE_4X (0 << 18)
54 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
57 # define TV_FUSE_STATE_ENABLED (0 << 4)
63 # define TV_TEST_MODE_NORMAL (0 << 0)
65 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
67 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
69 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
71 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
[all …]
/openbmc/qemu/tests/tcg/mips/include/
H A Dtest_inputs_32.h32 0xFFFFFFFF, /* 0 */
33 0x00000000,
34 0xAAAAAAAA,
35 0x55555555,
36 0xCCCCCCCC,
37 0x33333333,
38 0xE38E38E3,
39 0x1C71C71C,
40 0xF0F0F0F0, /* 8 */
41 0x0F0F0F0F,
[all …]
/openbmc/linux/drivers/net/ethernet/smsc/
H A Dsmsc911x.h12 #define LAN9115 0x01150000
13 #define LAN9116 0x01160000
14 #define LAN9117 0x01170000
15 #define LAN9118 0x01180000
16 #define LAN9215 0x115A0000
17 #define LAN9216 0x116A0000
18 #define LAN9217 0x117A0000
19 #define LAN9218 0x118A0000
20 #define LAN9210 0x92100000
21 #define LAN9211 0x92110000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_4_0_default.h26 #define mmVCE_STATUS_DEFAULT 0x00000000
27 #define mmVCE_VCPU_CNTL_DEFAULT 0x00200000
28 #define mmVCE_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
29 #define mmVCE_VCPU_CACHE_SIZE0_DEFAULT 0x00000000
30 #define mmVCE_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000
31 #define mmVCE_VCPU_CACHE_SIZE1_DEFAULT 0x00000000
32 #define mmVCE_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000
33 #define mmVCE_VCPU_CACHE_SIZE2_DEFAULT 0x00000000
34 #define mmVCE_VCPU_CACHE_OFFSET3_DEFAULT 0x00000000
35 #define mmVCE_VCPU_CACHE_SIZE3_DEFAULT 0x00000000
[all …]
/openbmc/linux/drivers/media/platform/nxp/
H A Dimx-pxp.h13 #define HW_PXP_CTRL (0x00000000)
14 #define HW_PXP_CTRL_SET (0x00000004)
15 #define HW_PXP_CTRL_CLR (0x00000008)
16 #define HW_PXP_CTRL_TOG (0x0000000c)
18 #define BM_PXP_CTRL_SFTRST 0x80000000
21 #define BM_PXP_CTRL_CLKGATE 0x40000000
24 #define BM_PXP_CTRL_RSVD4 0x20000000
27 #define BM_PXP_CTRL_EN_REPEAT 0x10000000
30 #define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000
33 #define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000
[all …]
/openbmc/linux/arch/x86/math-emu/
H A Dreg_round.S46 | extension (%edx) must contain 0, otherwise the significand extension |
53 | less than 0x80000000 <=> the significand is less than 1/2 an ls |
56 | exactly 0x80000000 <=> the significand is exactly 1/2 an ls bit |
59 | greater than 0x80000000 <=> the significand is more than 1/2 an ls |
99 .align 4,0
101 .byte 0
103 .byte 0
140 movb $0,FPU_denormal /* 0 -> not a de-normal */
143 movb $0,FPU_bits_lost /* No bits yet lost in rounding */
203 andl $0x000000ff,%ecx
[all …]
/openbmc/u-boot/drivers/net/
H A Dlpc32xx_eth.c40 #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
41 #define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800
42 #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
53 #define RX_STAT_RXSIZE 0x000007FF
55 #define RX_STAT_ERRORS 0x1B800000
66 #define TX_CTRL_TXSIZE 0x000007FF
67 #define TX_CTRL_LAST 0x40000000
78 /* MAC registers - 0x3106_0000 to 0x3106_01FC */
94 u32 sa0; /* Station address register 0 */
112 u32 tsv0; /* Transmit status vector register 0 */
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dphy.c23 } while (0)
33 return 0; in _rtl8821ae_phy_calculate_bit_shift()
60 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3); in rtl8812ae_fixspur()
61 /* 0x8AC[11:10] = 2'b11*/ in rtl8812ae_fixspur()
63 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2); in rtl8812ae_fixspur()
64 /* 0x8AC[11:10] = 2'b10*/ in rtl8812ae_fixspur()
71 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3); in rtl8812ae_fixspur()
72 /*0x8AC[9:8] = 2'b11*/ in rtl8812ae_fixspur()
74 /* 0x8C4[30] = 1*/ in rtl8812ae_fixspur()
78 /*0x8C4[30] = 1*/ in rtl8812ae_fixspur()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_diag.c17 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF in i40e_diag_reg_pattern_test()
23 for (i = 0; i < ARRAY_SIZE(patterns); i++) { in i40e_diag_reg_pattern_test()
29 "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n", in i40e_diag_reg_pattern_test()
39 "%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n", in i40e_diag_reg_pattern_test()
44 return 0; in i40e_diag_reg_pattern_test()
49 {I40E_QTX_CTL(0), 0x0000FFBF, 1,
50 I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
51 {I40E_PFINT_ITR0(0), 0x00000FFF, 3,
52 I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
53 {I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1,
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
/openbmc/linux/drivers/net/ethernet/sun/
H A Dsunbmac.h12 #define GLOB_CTRL 0x00UL /* Control */
13 #define GLOB_STAT 0x04UL /* Status */
14 #define GLOB_PSIZE 0x08UL /* Packet Size */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
16 #define GLOB_RSIZE 0x10UL /* Receive partition size */
17 #define GLOB_TSIZE 0x14UL /* Transmit partition size */
18 #define GLOB_REG_SIZE 0x18UL
20 #define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */
21 #define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */
22 #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */
[all …]
/openbmc/qemu/hw/sh4/
H A Dsh7750.c102 EVENPORTMASK(0); in portdir()
113 ODDPORTMASK(1) | ODDPORTMASK(0); in portpullup()
158 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") not supported\n", in error_access()
164 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") ignored\n", in ignore_access()
190 return 0; in sh7750_mem_readw()
205 return 0; in sh7750_mem_readw()
230 return 0; in sh7750_mem_readl()
249 case 0x1f000030: /* Processor version */ in sh7750_mem_readl()
252 case 0x1f000040: /* Cache version */ in sh7750_mem_readl()
255 case 0x1f000044: /* Processor revision */ in sh7750_mem_readl()
[all …]

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