Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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cde578ff |
| 09-Dec-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: restore license information in mv_ddr_plat.{c,h}
This was unintentionally removed when syncing with upstream.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
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8cb8c0c6 |
| 09-Dec-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-marvell
- Sync DDR training with Marvell code for Armada 38x by Chris - Misc updates to Armada 38x Helios4 board by Aditya
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ebb1a593 |
| 02-Dec-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-m
ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to release armada-18.09.2").
The complete log of changes is best obtained from the mv-ddr-marvell.git repository but some relevant highlights are:
ddr3: add missing txsdll parameter ddr3: fix tfaw timimg parameter ddr3: fix trrd timimg parameter merge ddr3 topology header file with mv_ddr_topology one mv_ddr: a38x: fix zero memory size scrubbing issue
The upstream code is incorporated omitting the portions not relevant to Armada-38x and DDR3. After that a semi-automated step is used to drop unused features with unifdef
find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \ -UA70X0
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
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Revision tags: v2018.07 |
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ca70cbab |
| 14-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-marvell
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db363dbc |
| 09-May-2018 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
ARM: mvebu: a38x: use non-zero size for ddr scrubbing
Make ddr3_calc_mem_cs_size() global scope and use it in ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris
ARM: mvebu: a38x: use non-zero size for ddr scrubbing
Make ddr3_calc_mem_cs_size() global scope and use it in ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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2b4ffbf6 |
| 09-May-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: a38x: sync ddr training code with upstream
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
T
ARM: mvebu: a38x: sync ddr training code with upstream
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef
find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT
INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.
Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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