1 #ifndef _MV_DDR_PLAT_H 2 #define _MV_DDR_PLAT_H 3 4 #define MAX_DEVICE_NUM 1 5 #define MAX_INTERFACE_NUM 1 6 #define MAX_BUS_NUM 5 7 #define DDR_IF_CTRL_SUBPHYS_NUM 3 8 9 #define DFS_LOW_FREQ_VALUE 120 10 #define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */ 11 12 #define INTER_REGS_BASE SOC_REGS_PHY_BASE 13 #define AP_INT_REG_START_ADDR 0xd0000000 14 #define AP_INT_REG_END_ADDR 0xd0100000 15 16 /* Controler bus divider 1 for 32 bit, 2 for 64 bit */ 17 #define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1 18 19 /* Tune internal training params values */ 20 #define TUNE_TRAINING_PARAMS_CK_DELAY 160 21 #define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xA 22 #define TUNE_TRAINING_PARAMS_PRI_DATA 123 23 #define TUNE_TRAINING_PARAMS_NRI_DATA 123 24 #define TUNE_TRAINING_PARAMS_PRI_CTRL 74 25 #define TUNE_TRAINING_PARAMS_NRI_CTRL 74 26 #define TUNE_TRAINING_PARAMS_P_ODT_DATA 45 27 #define TUNE_TRAINING_PARAMS_N_ODT_DATA 45 28 #define TUNE_TRAINING_PARAMS_P_ODT_CTRL 45 29 #define TUNE_TRAINING_PARAMS_N_ODT_CTRL 45 30 #define TUNE_TRAINING_PARAMS_DIC 0x2 31 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS 0x120012 32 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x10000 33 #define TUNE_TRAINING_PARAMS_RTT_NOM 0x44 34 35 #define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x0 /*off*/ 36 #define TUNE_TRAINING_PARAMS_RTT_WR_2CS 0x0 /*off*/ 37 38 #define MARVELL_BOARD MARVELL_BOARD_ID_BASE 39 40 41 #define REG_DEVICE_SAR1_ADDR 0xe4204 42 #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17 43 #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f 44 #define DEVICE_SAMPLE_AT_RESET2_REG 0x18604 45 46 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET 0 47 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ 0 48 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_40MHZ 1 49 50 /* DRAM Windows */ 51 #define REG_XBAR_WIN_5_CTRL_ADDR 0x20050 52 #define REG_XBAR_WIN_5_BASE_ADDR 0x20054 53 54 /* DRAM Windows */ 55 #define REG_XBAR_WIN_4_CTRL_ADDR 0x20040 56 #define REG_XBAR_WIN_4_BASE_ADDR 0x20044 57 #define REG_XBAR_WIN_4_REMAP_ADDR 0x20048 58 #define REG_XBAR_WIN_7_REMAP_ADDR 0x20078 59 #define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0 60 #define REG_XBAR_WIN_16_BASE_ADDR 0x200d4 61 #define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc 62 #define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8 63 64 #define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win)) 65 #define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win)) 66 67 #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) 68 #define CPU_MRVL_ID_OFFSET 0x10 69 #define SAR1_CPU_CORE_MASK 0x00000018 70 #define SAR1_CPU_CORE_OFFSET 3 71 72 /* SatR defined too change topology busWidth and ECC configuration */ 73 #define DDR_SATR_CONFIG_MASK_WIDTH 0x8 74 #define DDR_SATR_CONFIG_MASK_ECC 0x10 75 #define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20 76 77 #define REG_SAMPLE_RESET_HIGH_ADDR 0x18600 78 79 #define MV_BOARD_REFCLK_25MHZ 25000000 80 #define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ 81 82 #define MAX_DQ_NUM 40 83 84 /* dram line buffer registers */ 85 #define DLB_CTRL_REG 0x1700 86 #define DLB_EN_OFFS 0 87 #define DLB_EN_MASK 0x1 88 #define DLB_EN_ENA 1 89 #define DLB_EN_DIS 0 90 #define WR_COALESCE_EN_OFFS 2 91 #define WR_COALESCE_EN_MASK 0x1 92 #define WR_COALESCE_EN_ENA 1 93 #define WR_COALESCE_EN_DIS 0 94 #define AXI_PREFETCH_EN_OFFS 3 95 #define AXI_PREFETCH_EN_MASK 0x1 96 #define AXI_PREFETCH_EN_ENA 1 97 #define AXI_PREFETCH_EN_DIS 0 98 #define MBUS_PREFETCH_EN_OFFS 4 99 #define MBUS_PREFETCH_EN_MASK 0x1 100 #define MBUS_PREFETCH_EN_ENA 1 101 #define MBUS_PREFETCH_EN_DIS 0 102 #define PREFETCH_NXT_LN_SZ_TRIG_OFFS 6 103 #define PREFETCH_NXT_LN_SZ_TRIG_MASK 0x1 104 #define PREFETCH_NXT_LN_SZ_TRIG_ENA 1 105 #define PREFETCH_NXT_LN_SZ_TRIG_DIS 0 106 107 #define DLB_BUS_OPT_WT_REG 0x1704 108 #define DLB_AGING_REG 0x1708 109 #define DLB_EVICTION_CTRL_REG 0x170c 110 #define DLB_EVICTION_TIMERS_REG 0x1710 111 #define DLB_USER_CMD_REG 0x1714 112 #define DLB_WTS_DIFF_CS_REG 0x1770 113 #define DLB_WTS_DIFF_BG_REG 0x1774 114 #define DLB_WTS_SAME_BG_REG 0x1778 115 #define DLB_WTS_CMDS_REG 0x177c 116 #define DLB_WTS_ATTR_PRIO_REG 0x1780 117 #define DLB_QUEUE_MAP_REG 0x1784 118 #define DLB_SPLIT_REG 0x1788 119 120 /* ck swap control subphy number */ 121 #define CK_SWAP_CTRL_PHY_NUM 2 122 123 /* Subphy result control per byte registers */ 124 #define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830 125 #define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834 126 #define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838 127 #define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c 128 #define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0 129 130 /* Subphy result control per bit registers */ 131 #define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4 132 #define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8 133 #define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc 134 #define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0 135 #define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4 136 #define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8 137 #define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc 138 #define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0 139 140 #define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4 141 #define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8 142 #define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc 143 #define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930 144 #define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934 145 #define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938 146 #define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c 147 #define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0 148 149 #define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4 150 #define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8 151 #define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc 152 #define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0 153 #define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4 154 #define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8 155 #define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc 156 #define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0 157 158 #define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4 159 #define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8 160 #define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc 161 #define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30 162 #define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34 163 #define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38 164 #define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c 165 #define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0 166 167 #define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4 168 #define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8 169 #define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc 170 #define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0 171 #define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4 172 #define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8 173 #define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc 174 #define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0 175 176 /* CPU */ 177 #define REG_BOOTROM_ROUTINE_ADDR 0x182d0 178 #define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12 179 180 /* Matrix enables DRAM modes (bus width/ECC) per boardId */ 181 #define TOPOLOGY_UPDATE_32BIT 0 182 #define TOPOLOGY_UPDATE_32BIT_ECC 1 183 #define TOPOLOGY_UPDATE_16BIT 2 184 #define TOPOLOGY_UPDATE_16BIT_ECC 3 185 #define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4 186 #define TOPOLOGY_UPDATE { \ 187 /* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \ 188 {1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \ 189 {1, 1, 1, 1, 1}, /* DB_68XX_ID */ \ 190 {1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \ 191 {1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \ 192 {1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \ 193 {0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \ 194 {1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \ 195 }; 196 197 enum { 198 CPU_1066MHZ_DDR_400MHZ, 199 CPU_RESERVED_DDR_RESERVED0, 200 CPU_667MHZ_DDR_667MHZ, 201 CPU_800MHZ_DDR_800MHZ, 202 CPU_RESERVED_DDR_RESERVED1, 203 CPU_RESERVED_DDR_RESERVED2, 204 CPU_RESERVED_DDR_RESERVED3, 205 LAST_FREQ 206 }; 207 208 /* struct used for DLB configuration array */ 209 struct dlb_config { 210 u32 reg_addr; 211 u32 reg_data; 212 }; 213 214 #define ACTIVE_INTERFACE_MASK 0x1 215 216 extern u32 dmin_phy_reg_table[][2]; 217 extern u16 odt_slope[]; 218 extern u16 odt_intercept[]; 219 220 int mv_ddr_pre_training_soc_config(const char *ddr_type); 221 int mv_ddr_post_training_soc_config(const char *ddr_type); 222 void mv_ddr_mem_scrubbing(void); 223 u32 mv_ddr_init_freq_get(void); 224 void mv_ddr_odpg_enable(void); 225 void mv_ddr_odpg_disable(void); 226 void mv_ddr_odpg_done_clr(void); 227 int mv_ddr_is_odpg_done(u32 count); 228 void mv_ddr_training_enable(void); 229 int mv_ddr_is_training_done(u32 count, u32 *result); 230 u32 mv_ddr_dm_pad_get(void); 231 int mv_ddr_pre_training_fixup(void); 232 int mv_ddr_post_training_fixup(void); 233 int mv_ddr_manual_cal_do(void); 234 int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size); 235 236 #endif /* _MV_DDR_PLAT_H */ 237