History log of /openbmc/u-boot/arch/arm/mach-socfpga/misc_arria10.c (Results 1 – 18 of 18)
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# 5c676780 21-Dec-2018 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- stratix10 updates


# 877ec6eb 19-Dec-2018 Ang, Chee Hong <chee.hong.ang@intel.com>

arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.

Signed-off-by: An

arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table

Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>

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# a376702f 24-Aug-2018 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga


# 0b8f6378 18-Aug-2018 Marek Vasut <marex@denx.de>

ARM: socfpga: Reorder Arria10 SPL

The Arria10 SPL is a complete mess of calls to functions which are
called in the wrong context and it is surprise it works at all. This
patch tries to clean that me

ARM: socfpga: Reorder Arria10 SPL

The Arria10 SPL is a complete mess of calls to functions which are
called in the wrong context and it is surprise it works at all. This
patch tries to clean that mess up by shuffling the function calls
around and moving the calls into the correct context. Due to the
delicate nature of the reordering, this is done in one huge patch.

The following changes happen in this patch:
- Security policy init and NIC301 happens first in board_init_f()
- The clock init happens very early in board_init_f() in SPL only
- arch_early_init_r() only registers the FPGA, just like on Gen5
- arch_early_init_r() is never called from any _f() function
- Dedicated FPGA pins are inited in board_init_f() as on Gen5

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

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# 719afeb0 17-Aug-2018 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga


# d6a61da4 13-Aug-2018 Marek Vasut <marex@denx.de>

ARM: socfpga: Remove adhoc ethernet reset and configuration

Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon regist

ARM: socfpga: Remove adhoc ethernet reset and configuration

Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

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Revision tags: v2018.07
# f9edeb32 15-Apr-2018 Marek Vasut <marex@denx.de>

ARM: socfpga: Zap all the UART handling complexity

The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and consol

ARM: socfpga: Zap all the UART handling complexity

The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and console framework. Nuke all this comlexity, since it is just
duplicating the same functionality, badly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

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# ff6bef48 26-Jul-2018 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga


# 42f4b83b 12-Jul-2018 Marek Vasut <marex@denx.de>

ARM: socfpga: Init missing security policies on A10

The Arria10 requires proper configuration of the NOC firewall, otherwise
the access to certain areas of the LWHPS bridge fails in Linux. Add the
m

ARM: socfpga: Init missing security policies on A10

The Arria10 requires proper configuration of the NOC firewall, otherwise
the access to certain areas of the LWHPS bridge fails in Linux. Add the
missing setup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

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# 914bb7ea 13-Jul-2018 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c

Signed-off-by: Tom Rini <trini@konsulko.com>


# 2e1de5bd 01-Jun-2018 Ley Foon Tan <ley.foon.tan@intel.com>

arm: socfpga: Add do_bridge_reset for Arria 10

Add do_bridge_reset() function for Arria 10, it is required by misc.c.

arch/arm/mach-socfpga/built-in.o: In function `do_bridge':
arch/arm/mach-socfpg

arm: socfpga: Add do_bridge_reset for Arria 10

Add do_bridge_reset() function for Arria 10, it is required by misc.c.

arch/arm/mach-socfpga/built-in.o: In function `do_bridge':
arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset'
make[1]: *** [u-boot] Error 1

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

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# 904e5469 20-May-2018 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga


Revision tags: v2018.03, v2018.01
# 011fa5f3 05-Dec-2017 Tien Fong Chee <tien.fong.chee@intel.com>

ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot

SoC FPGA info is required in both SPL and U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>


# 32f99757 23-Apr-2018 Marek Vasut <marex@denx.de>

ARM: socfpga: Repair A10 EMAC reset handling

The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the

ARM: socfpga: Repair A10 EMAC reset handling

The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>

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# 83d290c5 06-May-2018 Tom Rini <trini@konsulko.com>

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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# d024236e 18-Apr-2018 Tom Rini <trini@konsulko.com>

Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR

We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added

Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR

We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>

show more ...


Revision tags: v2017.11
# 753a4dde 18-May-2017 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga


# 35b9800f 25-Apr-2017 Ley Foon Tan <ley.foon.tan@intel.com>

arm: socfpga: Add misc support for Arria 10

Add misc support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>