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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01 |
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baa29d5e |
| 18-Jul-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
Merge remote-tracking branch 'origin/aspeed-dev-v2019.04' into aspeed-master-v2019.04
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Revision tags: v2019.07, v00.02.00 |
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9da3b6f0 |
| 13-Jun-2019 |
Johnny Huang <johnny_huang@aspeedtech.com> |
Merge branch 'aspeed-dev-v2019.04' into aspeed-master-v2019.04
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a3e1b38c |
| 12-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04
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f51926ee |
| 12-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
add emmc/sd in ast2600
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e599f2e0 |
| 11-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04
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39f94504 |
| 10-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
enable i2c
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99357bac |
| 10-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
update for clk in dtsi and update ast2500 uart clk
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ac509baf |
| 09-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04
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86f91560 |
| 06-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
modify for mac clk
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e7135dfc |
| 05-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04
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39283ea7 |
| 05-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
update for reset and clk
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f0d895af |
| 30-May-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
update for clk
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5a5499fb |
| 30-May-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04
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d1e64dd1 |
| 29-May-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
modify clk
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3f781edc |
| 28-May-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
modify ast2500-scu.h -> ast2500-clock.h
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cbb554c3 |
| 22-May-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04
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d6e349c7 |
| 22-May-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
update clk
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Revision tags: v2019.04, v2018.07, v2018.03, v2018.01, v2017.11 |
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4f66e09b |
| 09-May-2017 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
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d5c16d00 |
| 17-Apr-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Gla
aspeed: Cleanup ast2500-u-boot.dtsi Device Tree
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
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3b95902d |
| 17-Apr-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 an
aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.
The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.
So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
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| #
c93adc08 |
| 17-Apr-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Device Tree configuration for Reset Driver
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko <maxims@google.com>
R
aspeed: Device Tree configuration for Reset Driver
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
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14e4b149 |
| 18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add basic ast2500-specific drivers and configuration
Clock Driver
This driver is ast2500-specific and is not compatible with earlier
versions of this chip. The differences are not that big,
aspeed: Add basic ast2500-specific drivers and configuration
Clock Driver
This driver is ast2500-specific and is not compatible with earlier
versions of this chip. The differences are not that big, but they are
in somewhat random places, so making it compatible with ast2400 is not
worth the effort at the moment.
SDRAM MC driver
The driver is very ast2500-specific and is completely incompatible
with previous versions of the chip.
The memory controller is very poorly documented by Aspeed in the
datasheet, with any mention of the whole range of registers missing. The
initialization procedure has been basically taken from Aspeed SDK, where
it is implemented in assembly. Here it is rewritten in C, with very limited
understanding of what exactly it is doing.
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
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