1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu.h" 23 #include "user-internals.h" 24 #include "cpu_loop-common.h" 25 #include "signal-common.h" 26 #include "elf.h" 27 #include "internal.h" 28 #include "fpu_helper.h" 29 30 # ifdef TARGET_ABI_MIPSO32 31 # define MIPS_SYSCALL_NUMBER_UNUSED -1 32 static const int8_t mips_syscall_args[] = { 33 #include "syscall-args-o32.c.inc" 34 }; 35 # endif /* O32 */ 36 37 /* Break codes */ 38 enum { 39 BRK_OVERFLOW = 6, 40 BRK_DIVZERO = 7 41 }; 42 43 static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap) 44 { 45 target_ulong pc = env->active_tc.PC; 46 47 switch (code) { 48 case BRK_OVERFLOW: 49 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, pc); 50 break; 51 case BRK_DIVZERO: 52 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, pc); 53 break; 54 default: 55 if (trap) { 56 force_sig(TARGET_SIGTRAP); 57 } else { 58 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, pc); 59 } 60 break; 61 } 62 } 63 64 void cpu_loop(CPUMIPSState *env) 65 { 66 CPUState *cs = env_cpu(env); 67 target_siginfo_t info; 68 int trapnr; 69 abi_long ret; 70 # ifdef TARGET_ABI_MIPSO32 71 unsigned int syscall_num; 72 # endif 73 74 for(;;) { 75 cpu_exec_start(cs); 76 trapnr = cpu_exec(cs); 77 cpu_exec_end(cs); 78 process_queued_cpu_work(cs); 79 80 switch(trapnr) { 81 case EXCP_SYSCALL: 82 env->active_tc.PC += 4; 83 # ifdef TARGET_ABI_MIPSO32 84 syscall_num = env->active_tc.gpr[2] - 4000; 85 if (syscall_num >= sizeof(mips_syscall_args)) { 86 /* syscall_num is larger that any defined for MIPS O32 */ 87 ret = -TARGET_ENOSYS; 88 } else if (mips_syscall_args[syscall_num] == 89 MIPS_SYSCALL_NUMBER_UNUSED) { 90 /* syscall_num belongs to the range not defined for MIPS O32 */ 91 ret = -TARGET_ENOSYS; 92 } else { 93 /* syscall_num is valid */ 94 int nb_args; 95 abi_ulong sp_reg; 96 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 97 98 nb_args = mips_syscall_args[syscall_num]; 99 sp_reg = env->active_tc.gpr[29]; 100 switch (nb_args) { 101 /* these arguments are taken from the stack */ 102 case 8: 103 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 104 goto done_syscall; 105 } 106 /* fall through */ 107 case 7: 108 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 109 goto done_syscall; 110 } 111 /* fall through */ 112 case 6: 113 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 114 goto done_syscall; 115 } 116 /* fall through */ 117 case 5: 118 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 119 goto done_syscall; 120 } 121 /* fall through */ 122 default: 123 break; 124 } 125 ret = do_syscall(env, env->active_tc.gpr[2], 126 env->active_tc.gpr[4], 127 env->active_tc.gpr[5], 128 env->active_tc.gpr[6], 129 env->active_tc.gpr[7], 130 arg5, arg6, arg7, arg8); 131 } 132 done_syscall: 133 # else 134 ret = do_syscall(env, env->active_tc.gpr[2], 135 env->active_tc.gpr[4], env->active_tc.gpr[5], 136 env->active_tc.gpr[6], env->active_tc.gpr[7], 137 env->active_tc.gpr[8], env->active_tc.gpr[9], 138 env->active_tc.gpr[10], env->active_tc.gpr[11]); 139 # endif /* O32 */ 140 if (ret == -QEMU_ERESTARTSYS) { 141 env->active_tc.PC -= 4; 142 break; 143 } 144 if (ret == -QEMU_ESIGRETURN) { 145 /* Returning from a successful sigreturn syscall. 146 Avoid clobbering register state. */ 147 break; 148 } 149 if ((abi_ulong)ret >= (abi_ulong)-1133) { 150 env->active_tc.gpr[7] = 1; /* error flag */ 151 ret = -ret; 152 } else { 153 env->active_tc.gpr[7] = 0; /* error flag */ 154 } 155 env->active_tc.gpr[2] = ret; 156 break; 157 case EXCP_CpU: 158 case EXCP_RI: 159 info.si_signo = TARGET_SIGILL; 160 info.si_errno = 0; 161 info.si_code = 0; 162 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 163 break; 164 case EXCP_INTERRUPT: 165 /* just indicate that signals should be handled asap */ 166 break; 167 case EXCP_DEBUG: 168 info.si_signo = TARGET_SIGTRAP; 169 info.si_errno = 0; 170 info.si_code = TARGET_TRAP_BRKPT; 171 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 172 break; 173 case EXCP_DSPDIS: 174 info.si_signo = TARGET_SIGILL; 175 info.si_errno = 0; 176 info.si_code = TARGET_ILL_ILLOPC; 177 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 178 break; 179 case EXCP_FPE: 180 info.si_signo = TARGET_SIGFPE; 181 info.si_errno = 0; 182 info.si_code = TARGET_FPE_FLTUNK; 183 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { 184 info.si_code = TARGET_FPE_FLTINV; 185 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) { 186 info.si_code = TARGET_FPE_FLTDIV; 187 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) { 188 info.si_code = TARGET_FPE_FLTOVF; 189 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) { 190 info.si_code = TARGET_FPE_FLTUND; 191 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) { 192 info.si_code = TARGET_FPE_FLTRES; 193 } 194 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 195 break; 196 /* The code below was inspired by the MIPS Linux kernel trap 197 * handling code in arch/mips/kernel/traps.c. 198 */ 199 case EXCP_BREAK: 200 { 201 abi_ulong trap_instr; 202 unsigned int code; 203 204 /* 205 * FIXME: It would be better to decode the trap number 206 * during translate, and store it in error_code while 207 * raising the exception. We should not be re-reading 208 * the opcode here. 209 */ 210 211 if (env->hflags & MIPS_HFLAG_M16) { 212 if (env->insn_flags & ASE_MICROMIPS) { 213 /* microMIPS mode */ 214 ret = get_user_u16(trap_instr, env->active_tc.PC); 215 if (ret != 0) { 216 goto error; 217 } 218 219 if ((trap_instr >> 10) == 0x11) { 220 /* 16-bit instruction */ 221 code = trap_instr & 0xf; 222 } else { 223 /* 32-bit instruction */ 224 abi_ulong instr_lo; 225 226 ret = get_user_u16(instr_lo, 227 env->active_tc.PC + 2); 228 if (ret != 0) { 229 goto error; 230 } 231 trap_instr = (trap_instr << 16) | instr_lo; 232 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 233 /* Unfortunately, microMIPS also suffers from 234 the old assembler bug... */ 235 if (code >= (1 << 10)) { 236 code >>= 10; 237 } 238 } 239 } else { 240 /* MIPS16e mode */ 241 ret = get_user_u16(trap_instr, env->active_tc.PC); 242 if (ret != 0) { 243 goto error; 244 } 245 code = (trap_instr >> 6) & 0x3f; 246 } 247 } else { 248 ret = get_user_u32(trap_instr, env->active_tc.PC); 249 if (ret != 0) { 250 goto error; 251 } 252 253 /* As described in the original Linux kernel code, the 254 * below checks on 'code' are to work around an old 255 * assembly bug. 256 */ 257 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 258 if (code >= (1 << 10)) { 259 code >>= 10; 260 } 261 } 262 263 do_tr_or_bp(env, code, false); 264 } 265 break; 266 case EXCP_TRAP: 267 { 268 abi_ulong trap_instr; 269 unsigned int code = 0; 270 271 /* 272 * FIXME: It would be better to decode the trap number 273 * during translate, and store it in error_code while 274 * raising the exception. We should not be re-reading 275 * the opcode here. 276 */ 277 278 if (env->hflags & MIPS_HFLAG_M16) { 279 /* microMIPS mode */ 280 abi_ulong instr[2]; 281 282 ret = get_user_u16(instr[0], env->active_tc.PC) || 283 get_user_u16(instr[1], env->active_tc.PC + 2); 284 285 trap_instr = (instr[0] << 16) | instr[1]; 286 } else { 287 ret = get_user_u32(trap_instr, env->active_tc.PC); 288 } 289 290 if (ret != 0) { 291 goto error; 292 } 293 294 /* The immediate versions don't provide a code. */ 295 if (!(trap_instr & 0xFC000000)) { 296 if (env->hflags & MIPS_HFLAG_M16) { 297 /* microMIPS mode */ 298 code = ((trap_instr >> 12) & ((1 << 4) - 1)); 299 } else { 300 code = ((trap_instr >> 6) & ((1 << 10) - 1)); 301 } 302 } 303 304 do_tr_or_bp(env, code, true); 305 } 306 break; 307 case EXCP_ATOMIC: 308 cpu_exec_step_atomic(cs); 309 break; 310 default: 311 error: 312 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 313 abort(); 314 } 315 process_pending_signals(env); 316 } 317 } 318 319 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 320 { 321 CPUState *cpu = env_cpu(env); 322 TaskState *ts = cpu->opaque; 323 struct image_info *info = ts->info; 324 int i; 325 326 struct mode_req { 327 bool single; 328 bool soft; 329 bool fr1; 330 bool frdefault; 331 bool fre; 332 }; 333 334 static const struct mode_req fpu_reqs[] = { 335 [MIPS_ABI_FP_ANY] = { true, true, true, true, true }, 336 [MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true }, 337 [MIPS_ABI_FP_SINGLE] = { true, false, false, false, false }, 338 [MIPS_ABI_FP_SOFT] = { false, true, false, false, false }, 339 [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false }, 340 [MIPS_ABI_FP_XX] = { false, false, true, true, true }, 341 [MIPS_ABI_FP_64] = { false, false, true, false, false }, 342 [MIPS_ABI_FP_64A] = { false, false, true, false, true } 343 }; 344 345 /* 346 * Mode requirements when .MIPS.abiflags is not present in the ELF. 347 * Not present means that everything is acceptable except FR1. 348 */ 349 static struct mode_req none_req = { true, true, false, true, true }; 350 351 struct mode_req prog_req; 352 struct mode_req interp_req; 353 354 for(i = 0; i < 32; i++) { 355 env->active_tc.gpr[i] = regs->regs[i]; 356 } 357 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 358 if (regs->cp0_epc & 1) { 359 env->hflags |= MIPS_HFLAG_M16; 360 } 361 362 #ifdef TARGET_ABI_MIPSO32 363 # define MAX_FP_ABI MIPS_ABI_FP_64A 364 #else 365 # define MAX_FP_ABI MIPS_ABI_FP_SOFT 366 #endif 367 if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN) 368 || (info->interp_fp_abi > MAX_FP_ABI && 369 info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) { 370 fprintf(stderr, "qemu: Unexpected FPU mode\n"); 371 exit(1); 372 } 373 374 prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req 375 : fpu_reqs[info->fp_abi]; 376 interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req 377 : fpu_reqs[info->interp_fp_abi]; 378 379 prog_req.single &= interp_req.single; 380 prog_req.soft &= interp_req.soft; 381 prog_req.fr1 &= interp_req.fr1; 382 prog_req.frdefault &= interp_req.frdefault; 383 prog_req.fre &= interp_req.fre; 384 385 bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 || 386 env->insn_flags & ISA_MIPS_R6; 387 388 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { 389 env->CP0_Config5 |= (1 << CP0C5_FRE); 390 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 391 env->hflags |= MIPS_HFLAG_FRE; 392 } 393 } else if ((prog_req.fr1 && prog_req.frdefault) || 394 (prog_req.single && !prog_req.frdefault)) { 395 if ((env->active_fpu.fcr0 & (1 << FCR0_F64) 396 && cpu_has_mips_r2_r6) || prog_req.fr1) { 397 env->CP0_Status |= (1 << CP0St_FR); 398 env->hflags |= MIPS_HFLAG_F64; 399 } 400 } else if (!prog_req.fre && !prog_req.frdefault && 401 !prog_req.fr1 && !prog_req.single && !prog_req.soft) { 402 fprintf(stderr, "qemu: Can't find a matching FPU mode\n"); 403 exit(1); 404 } 405 406 if (env->insn_flags & ISA_NANOMIPS32) { 407 return; 408 } 409 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != 410 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { 411 if ((env->active_fpu.fcr31_rw_bitmask & 412 (1 << FCR31_NAN2008)) == 0) { 413 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); 414 exit(1); 415 } 416 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { 417 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); 418 } else { 419 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); 420 } 421 restore_snan_bit_mode(env); 422 } 423 } 424