stm32-usart.c (25a8e7611da5513b388165661b17173c26e12c04) stm32-usart.c (ad7676812437a00a4c6be155fc17926069f99084)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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209 return c;
210}
211
212static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
213{
214 struct tty_port *tport = &port->state->port;
215 struct stm32_port *stm32_port = to_stm32_port(port);
216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *

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209 return c;
210}
211
212static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
213{
214 struct tty_port *tport = &port->state->port;
215 struct stm32_port *stm32_port = to_stm32_port(port);
216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
217 unsigned long c;
217 unsigned long c, flags;
218 u32 sr;
219 char flag;
220
221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
222 pm_wakeup_event(tport->tty->dev, 0);
223
218 u32 sr;
219 char flag;
220
221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
222 pm_wakeup_event(tport->tty->dev, 0);
223
224 if (threaded)
225 spin_lock_irqsave(&port->lock, flags);
226 else
227 spin_lock(&port->lock);
228
224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
225 threaded)) {
226 sr |= USART_SR_DUMMY_RX;
227 flag = TTY_NORMAL;
228
229 /*
230 * Status bits has to be cleared before reading the RDR:
231 * In FIFO mode, reading the RDR will pop the next data

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271 }
272 }
273
274 if (uart_handle_sysrq_char(port, c))
275 continue;
276 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
277 }
278
229 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
230 threaded)) {
231 sr |= USART_SR_DUMMY_RX;
232 flag = TTY_NORMAL;
233
234 /*
235 * Status bits has to be cleared before reading the RDR:
236 * In FIFO mode, reading the RDR will pop the next data

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276 }
277 }
278
279 if (uart_handle_sysrq_char(port, c))
280 continue;
281 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
282 }
283
279 spin_unlock(&port->lock);
284 if (threaded)
285 spin_unlock_irqrestore(&port->lock, flags);
286 else
287 spin_unlock(&port->lock);
288
280 tty_flip_buffer_push(tport);
289 tty_flip_buffer_push(tport);
281 spin_lock(&port->lock);
282}
283
284static void stm32_usart_tx_dma_complete(void *arg)
285{
286 struct uart_port *port = arg;
287 struct stm32_port *stm32port = to_stm32_port(port);
288 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
289

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454
455static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
456{
457 struct uart_port *port = ptr;
458 struct stm32_port *stm32_port = to_stm32_port(port);
459 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
460 u32 sr;
461
290}
291
292static void stm32_usart_tx_dma_complete(void *arg)
293{
294 struct uart_port *port = arg;
295 struct stm32_port *stm32port = to_stm32_port(port);
296 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
297

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462
463static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
464{
465 struct uart_port *port = ptr;
466 struct stm32_port *stm32_port = to_stm32_port(port);
467 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
468 u32 sr;
469
462 spin_lock(&port->lock);
463
464 sr = readl_relaxed(port->membase + ofs->isr);
465
466 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
467 writel_relaxed(USART_ICR_RTOCF,
468 port->membase + ofs->icr);
469
470 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG)
471 writel_relaxed(USART_ICR_WUCF,
472 port->membase + ofs->icr);
473
474 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
475 stm32_usart_receive_chars(port, false);
476
470 sr = readl_relaxed(port->membase + ofs->isr);
471
472 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
473 writel_relaxed(USART_ICR_RTOCF,
474 port->membase + ofs->icr);
475
476 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG)
477 writel_relaxed(USART_ICR_WUCF,
478 port->membase + ofs->icr);
479
480 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
481 stm32_usart_receive_chars(port, false);
482
477 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
483 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
484 spin_lock(&port->lock);
478 stm32_usart_transmit_chars(port);
485 stm32_usart_transmit_chars(port);
486 spin_unlock(&port->lock);
487 }
479
488
480 spin_unlock(&port->lock);
481
482 if (stm32_port->rx_ch)
483 return IRQ_WAKE_THREAD;
484 else
485 return IRQ_HANDLED;
486}
487
488static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
489{
490 struct uart_port *port = ptr;
491 struct stm32_port *stm32_port = to_stm32_port(port);
492
489 if (stm32_port->rx_ch)
490 return IRQ_WAKE_THREAD;
491 else
492 return IRQ_HANDLED;
493}
494
495static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
496{
497 struct uart_port *port = ptr;
498 struct stm32_port *stm32_port = to_stm32_port(port);
499
493 spin_lock(&port->lock);
494
495 if (stm32_port->rx_ch)
496 stm32_usart_receive_chars(port, true);
497
500 if (stm32_port->rx_ch)
501 stm32_usart_receive_chars(port, true);
502
498 spin_unlock(&port->lock);
499
500 return IRQ_HANDLED;
501}
502
503static unsigned int stm32_usart_tx_empty(struct uart_port *port)
504{
505 struct stm32_port *stm32_port = to_stm32_port(port);
506 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
507

--- 1094 unchanged lines hidden --- 		503 return IRQ_HANDLED;
504}
505
506static unsigned int stm32_usart_tx_empty(struct uart_port *port)
507{
508 struct stm32_port *stm32_port = to_stm32_port(port);
509 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
510

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