1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 static void stm32_usart_stop_tx(struct uart_port *port); 39 static void stm32_usart_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 65 u32 delay_DDE, u32 baud) 66 { 67 u32 rs485_deat_dedt; 68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 69 bool over8; 70 71 *cr3 |= USART_CR3_DEM; 72 over8 = *cr1 & USART_CR1_OVER8; 73 74 if (over8) 75 rs485_deat_dedt = delay_ADE * baud * 8; 76 else 77 rs485_deat_dedt = delay_ADE * baud * 16; 78 79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 81 rs485_deat_dedt_max : rs485_deat_dedt; 82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 83 USART_CR1_DEAT_MASK; 84 *cr1 |= rs485_deat_dedt; 85 86 if (over8) 87 rs485_deat_dedt = delay_DDE * baud * 8; 88 else 89 rs485_deat_dedt = delay_DDE * baud * 16; 90 91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 93 rs485_deat_dedt_max : rs485_deat_dedt; 94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 95 USART_CR1_DEDT_MASK; 96 *cr1 |= rs485_deat_dedt; 97 } 98 99 static int stm32_usart_config_rs485(struct uart_port *port, 100 struct serial_rs485 *rs485conf) 101 { 102 struct stm32_port *stm32_port = to_stm32_port(port); 103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 105 u32 usartdiv, baud, cr1, cr3; 106 bool over8; 107 108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 109 110 port->rs485 = *rs485conf; 111 112 rs485conf->flags |= SER_RS485_RX_DURING_TX; 113 114 if (rs485conf->flags & SER_RS485_ENABLED) { 115 cr1 = readl_relaxed(port->membase + ofs->cr1); 116 cr3 = readl_relaxed(port->membase + ofs->cr3); 117 usartdiv = readl_relaxed(port->membase + ofs->brr); 118 usartdiv = usartdiv & GENMASK(15, 0); 119 over8 = cr1 & USART_CR1_OVER8; 120 121 if (over8) 122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 123 << USART_BRR_04_R_SHIFT; 124 125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 126 stm32_usart_config_reg_rs485(&cr1, &cr3, 127 rs485conf->delay_rts_before_send, 128 rs485conf->delay_rts_after_send, 129 baud); 130 131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 132 cr3 &= ~USART_CR3_DEP; 133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 134 } else { 135 cr3 |= USART_CR3_DEP; 136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 137 } 138 139 writel_relaxed(cr3, port->membase + ofs->cr3); 140 writel_relaxed(cr1, port->membase + ofs->cr1); 141 } else { 142 stm32_usart_clr_bits(port, ofs->cr3, 143 USART_CR3_DEM | USART_CR3_DEP); 144 stm32_usart_clr_bits(port, ofs->cr1, 145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 146 } 147 148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 149 150 return 0; 151 } 152 153 static int stm32_usart_init_rs485(struct uart_port *port, 154 struct platform_device *pdev) 155 { 156 struct serial_rs485 *rs485conf = &port->rs485; 157 158 rs485conf->flags = 0; 159 rs485conf->delay_rts_before_send = 0; 160 rs485conf->delay_rts_after_send = 0; 161 162 if (!pdev->dev.of_node) 163 return -ENODEV; 164 165 return uart_get_rs485_mode(port); 166 } 167 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 169 int *last_res, bool threaded) 170 { 171 struct stm32_port *stm32_port = to_stm32_port(port); 172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 173 enum dma_status status; 174 struct dma_tx_state state; 175 176 *sr = readl_relaxed(port->membase + ofs->isr); 177 178 if (threaded && stm32_port->rx_ch) { 179 status = dmaengine_tx_status(stm32_port->rx_ch, 180 stm32_port->rx_ch->cookie, 181 &state); 182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c; 218 u32 sr; 219 char flag; 220 221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 222 pm_wakeup_event(tport->tty->dev, 0); 223 224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 225 threaded)) { 226 sr |= USART_SR_DUMMY_RX; 227 flag = TTY_NORMAL; 228 229 /* 230 * Status bits has to be cleared before reading the RDR: 231 * In FIFO mode, reading the RDR will pop the next data 232 * (if any) along with its status bits into the SR. 233 * Not doing so leads to misalignement between RDR and SR, 234 * and clear status bits of the next rx data. 235 * 236 * Clear errors flags for stm32f7 and stm32h7 compatible 237 * devices. On stm32f4 compatible devices, the error bit is 238 * cleared by the sequence [read SR - read DR]. 239 */ 240 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 241 writel_relaxed(sr & USART_SR_ERR_MASK, 242 port->membase + ofs->icr); 243 244 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 245 port->icount.rx++; 246 if (sr & USART_SR_ERR_MASK) { 247 if (sr & USART_SR_ORE) { 248 port->icount.overrun++; 249 } else if (sr & USART_SR_PE) { 250 port->icount.parity++; 251 } else if (sr & USART_SR_FE) { 252 /* Break detection if character is null */ 253 if (!c) { 254 port->icount.brk++; 255 if (uart_handle_break(port)) 256 continue; 257 } else { 258 port->icount.frame++; 259 } 260 } 261 262 sr &= port->read_status_mask; 263 264 if (sr & USART_SR_PE) { 265 flag = TTY_PARITY; 266 } else if (sr & USART_SR_FE) { 267 if (!c) 268 flag = TTY_BREAK; 269 else 270 flag = TTY_FRAME; 271 } 272 } 273 274 if (uart_handle_sysrq_char(port, c)) 275 continue; 276 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 277 } 278 279 spin_unlock(&port->lock); 280 tty_flip_buffer_push(tport); 281 spin_lock(&port->lock); 282 } 283 284 static void stm32_usart_tx_dma_complete(void *arg) 285 { 286 struct uart_port *port = arg; 287 struct stm32_port *stm32port = to_stm32_port(port); 288 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 289 290 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 291 stm32port->tx_dma_busy = false; 292 293 /* Let's see if we have pending data to send */ 294 stm32_usart_transmit_chars(port); 295 } 296 297 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 298 { 299 struct stm32_port *stm32_port = to_stm32_port(port); 300 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 301 302 /* 303 * Enables TX FIFO threashold irq when FIFO is enabled, 304 * or TX empty irq when FIFO is disabled 305 */ 306 if (stm32_port->fifoen) 307 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 308 else 309 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 310 } 311 312 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 313 { 314 struct stm32_port *stm32_port = to_stm32_port(port); 315 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 316 317 if (stm32_port->fifoen) 318 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 319 else 320 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 321 } 322 323 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 324 { 325 struct stm32_port *stm32_port = to_stm32_port(port); 326 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 327 struct circ_buf *xmit = &port->state->xmit; 328 329 if (stm32_port->tx_dma_busy) { 330 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 331 stm32_port->tx_dma_busy = false; 332 } 333 334 while (!uart_circ_empty(xmit)) { 335 /* Check that TDR is empty before filling FIFO */ 336 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 337 break; 338 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 339 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 340 port->icount.tx++; 341 } 342 343 /* rely on TXE irq (mask or unmask) for sending remaining data */ 344 if (uart_circ_empty(xmit)) 345 stm32_usart_tx_interrupt_disable(port); 346 else 347 stm32_usart_tx_interrupt_enable(port); 348 } 349 350 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 351 { 352 struct stm32_port *stm32port = to_stm32_port(port); 353 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 354 struct circ_buf *xmit = &port->state->xmit; 355 struct dma_async_tx_descriptor *desc = NULL; 356 unsigned int count, i; 357 358 if (stm32port->tx_dma_busy) 359 return; 360 361 stm32port->tx_dma_busy = true; 362 363 count = uart_circ_chars_pending(xmit); 364 365 if (count > TX_BUF_L) 366 count = TX_BUF_L; 367 368 if (xmit->tail < xmit->head) { 369 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 370 } else { 371 size_t one = UART_XMIT_SIZE - xmit->tail; 372 size_t two; 373 374 if (one > count) 375 one = count; 376 two = count - one; 377 378 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 379 if (two) 380 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 381 } 382 383 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 384 stm32port->tx_dma_buf, 385 count, 386 DMA_MEM_TO_DEV, 387 DMA_PREP_INTERRUPT); 388 389 if (!desc) 390 goto fallback_err; 391 392 desc->callback = stm32_usart_tx_dma_complete; 393 desc->callback_param = port; 394 395 /* Push current DMA TX transaction in the pending queue */ 396 if (dma_submit_error(dmaengine_submit(desc))) { 397 /* dma no yet started, safe to free resources */ 398 dmaengine_terminate_async(stm32port->tx_ch); 399 goto fallback_err; 400 } 401 402 /* Issue pending DMA TX requests */ 403 dma_async_issue_pending(stm32port->tx_ch); 404 405 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 406 407 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 408 port->icount.tx += count; 409 return; 410 411 fallback_err: 412 for (i = count; i > 0; i--) 413 stm32_usart_transmit_chars_pio(port); 414 } 415 416 static void stm32_usart_transmit_chars(struct uart_port *port) 417 { 418 struct stm32_port *stm32_port = to_stm32_port(port); 419 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 420 struct circ_buf *xmit = &port->state->xmit; 421 422 if (port->x_char) { 423 if (stm32_port->tx_dma_busy) 424 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 425 writel_relaxed(port->x_char, port->membase + ofs->tdr); 426 port->x_char = 0; 427 port->icount.tx++; 428 if (stm32_port->tx_dma_busy) 429 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 430 return; 431 } 432 433 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 434 stm32_usart_tx_interrupt_disable(port); 435 return; 436 } 437 438 if (ofs->icr == UNDEF_REG) 439 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 440 else 441 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 442 443 if (stm32_port->tx_ch) 444 stm32_usart_transmit_chars_dma(port); 445 else 446 stm32_usart_transmit_chars_pio(port); 447 448 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 449 uart_write_wakeup(port); 450 451 if (uart_circ_empty(xmit)) 452 stm32_usart_tx_interrupt_disable(port); 453 } 454 455 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 456 { 457 struct uart_port *port = ptr; 458 struct stm32_port *stm32_port = to_stm32_port(port); 459 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 460 u32 sr; 461 462 spin_lock(&port->lock); 463 464 sr = readl_relaxed(port->membase + ofs->isr); 465 466 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 467 writel_relaxed(USART_ICR_RTOCF, 468 port->membase + ofs->icr); 469 470 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) 471 writel_relaxed(USART_ICR_WUCF, 472 port->membase + ofs->icr); 473 474 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 475 stm32_usart_receive_chars(port, false); 476 477 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) 478 stm32_usart_transmit_chars(port); 479 480 spin_unlock(&port->lock); 481 482 if (stm32_port->rx_ch) 483 return IRQ_WAKE_THREAD; 484 else 485 return IRQ_HANDLED; 486 } 487 488 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 489 { 490 struct uart_port *port = ptr; 491 struct stm32_port *stm32_port = to_stm32_port(port); 492 493 spin_lock(&port->lock); 494 495 if (stm32_port->rx_ch) 496 stm32_usart_receive_chars(port, true); 497 498 spin_unlock(&port->lock); 499 500 return IRQ_HANDLED; 501 } 502 503 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 504 { 505 struct stm32_port *stm32_port = to_stm32_port(port); 506 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 507 508 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 509 } 510 511 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 512 { 513 struct stm32_port *stm32_port = to_stm32_port(port); 514 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 515 516 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 517 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 518 else 519 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 520 521 mctrl_gpio_set(stm32_port->gpios, mctrl); 522 } 523 524 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 525 { 526 struct stm32_port *stm32_port = to_stm32_port(port); 527 unsigned int ret; 528 529 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 530 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 531 532 return mctrl_gpio_get(stm32_port->gpios, &ret); 533 } 534 535 static void stm32_usart_enable_ms(struct uart_port *port) 536 { 537 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 538 } 539 540 static void stm32_usart_disable_ms(struct uart_port *port) 541 { 542 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 543 } 544 545 /* Transmit stop */ 546 static void stm32_usart_stop_tx(struct uart_port *port) 547 { 548 struct stm32_port *stm32_port = to_stm32_port(port); 549 struct serial_rs485 *rs485conf = &port->rs485; 550 551 stm32_usart_tx_interrupt_disable(port); 552 553 if (rs485conf->flags & SER_RS485_ENABLED) { 554 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 555 mctrl_gpio_set(stm32_port->gpios, 556 stm32_port->port.mctrl & ~TIOCM_RTS); 557 } else { 558 mctrl_gpio_set(stm32_port->gpios, 559 stm32_port->port.mctrl | TIOCM_RTS); 560 } 561 } 562 } 563 564 /* There are probably characters waiting to be transmitted. */ 565 static void stm32_usart_start_tx(struct uart_port *port) 566 { 567 struct stm32_port *stm32_port = to_stm32_port(port); 568 struct serial_rs485 *rs485conf = &port->rs485; 569 struct circ_buf *xmit = &port->state->xmit; 570 571 if (uart_circ_empty(xmit)) 572 return; 573 574 if (rs485conf->flags & SER_RS485_ENABLED) { 575 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 576 mctrl_gpio_set(stm32_port->gpios, 577 stm32_port->port.mctrl | TIOCM_RTS); 578 } else { 579 mctrl_gpio_set(stm32_port->gpios, 580 stm32_port->port.mctrl & ~TIOCM_RTS); 581 } 582 } 583 584 stm32_usart_transmit_chars(port); 585 } 586 587 /* Throttle the remote when input buffer is about to overflow. */ 588 static void stm32_usart_throttle(struct uart_port *port) 589 { 590 struct stm32_port *stm32_port = to_stm32_port(port); 591 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 592 unsigned long flags; 593 594 spin_lock_irqsave(&port->lock, flags); 595 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 596 if (stm32_port->cr3_irq) 597 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 598 599 spin_unlock_irqrestore(&port->lock, flags); 600 } 601 602 /* Unthrottle the remote, the input buffer can now accept data. */ 603 static void stm32_usart_unthrottle(struct uart_port *port) 604 { 605 struct stm32_port *stm32_port = to_stm32_port(port); 606 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 607 unsigned long flags; 608 609 spin_lock_irqsave(&port->lock, flags); 610 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 611 if (stm32_port->cr3_irq) 612 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 613 614 spin_unlock_irqrestore(&port->lock, flags); 615 } 616 617 /* Receive stop */ 618 static void stm32_usart_stop_rx(struct uart_port *port) 619 { 620 struct stm32_port *stm32_port = to_stm32_port(port); 621 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 622 623 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 624 if (stm32_port->cr3_irq) 625 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 626 } 627 628 /* Handle breaks - ignored by us */ 629 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 630 { 631 } 632 633 static int stm32_usart_startup(struct uart_port *port) 634 { 635 struct stm32_port *stm32_port = to_stm32_port(port); 636 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 637 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 638 const char *name = to_platform_device(port->dev)->name; 639 u32 val; 640 int ret; 641 642 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 643 stm32_usart_threaded_interrupt, 644 IRQF_NO_SUSPEND, name, port); 645 if (ret) 646 return ret; 647 648 /* RX FIFO Flush */ 649 if (ofs->rqr != UNDEF_REG) 650 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); 651 652 /* RX enabling */ 653 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 654 stm32_usart_set_bits(port, ofs->cr1, val); 655 656 return 0; 657 } 658 659 static void stm32_usart_shutdown(struct uart_port *port) 660 { 661 struct stm32_port *stm32_port = to_stm32_port(port); 662 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 663 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 664 u32 val, isr; 665 int ret; 666 667 /* Disable modem control interrupts */ 668 stm32_usart_disable_ms(port); 669 670 val = USART_CR1_TXEIE | USART_CR1_TE; 671 val |= stm32_port->cr1_irq | USART_CR1_RE; 672 val |= BIT(cfg->uart_enable_bit); 673 if (stm32_port->fifoen) 674 val |= USART_CR1_FIFOEN; 675 676 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 677 isr, (isr & USART_SR_TC), 678 10, 100000); 679 680 /* Send the TC error message only when ISR_TC is not set */ 681 if (ret) 682 dev_err(port->dev, "Transmission is not complete\n"); 683 684 stm32_usart_clr_bits(port, ofs->cr1, val); 685 686 free_irq(port->irq, port); 687 } 688 689 static unsigned int stm32_usart_get_databits(struct ktermios *termios) 690 { 691 unsigned int bits; 692 693 tcflag_t cflag = termios->c_cflag; 694 695 switch (cflag & CSIZE) { 696 /* 697 * CSIZE settings are not necessarily supported in hardware. 698 * CSIZE unsupported configurations are handled here to set word length 699 * to 8 bits word as default configuration and to print debug message. 700 */ 701 case CS5: 702 bits = 5; 703 break; 704 case CS6: 705 bits = 6; 706 break; 707 case CS7: 708 bits = 7; 709 break; 710 /* default including CS8 */ 711 default: 712 bits = 8; 713 break; 714 } 715 716 return bits; 717 } 718 719 static void stm32_usart_set_termios(struct uart_port *port, 720 struct ktermios *termios, 721 struct ktermios *old) 722 { 723 struct stm32_port *stm32_port = to_stm32_port(port); 724 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 725 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 726 struct serial_rs485 *rs485conf = &port->rs485; 727 unsigned int baud, bits; 728 u32 usartdiv, mantissa, fraction, oversampling; 729 tcflag_t cflag = termios->c_cflag; 730 u32 cr1, cr2, cr3, isr; 731 unsigned long flags; 732 int ret; 733 734 if (!stm32_port->hw_flow_control) 735 cflag &= ~CRTSCTS; 736 737 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 738 739 spin_lock_irqsave(&port->lock, flags); 740 741 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 742 isr, 743 (isr & USART_SR_TC), 744 10, 100000); 745 746 /* Send the TC error message only when ISR_TC is not set. */ 747 if (ret) 748 dev_err(port->dev, "Transmission is not complete\n"); 749 750 /* Stop serial port and reset value */ 751 writel_relaxed(0, port->membase + ofs->cr1); 752 753 /* flush RX & TX FIFO */ 754 if (ofs->rqr != UNDEF_REG) 755 stm32_usart_set_bits(port, ofs->rqr, 756 USART_RQR_TXFRQ | USART_RQR_RXFRQ); 757 758 cr1 = USART_CR1_TE | USART_CR1_RE; 759 if (stm32_port->fifoen) 760 cr1 |= USART_CR1_FIFOEN; 761 cr2 = 0; 762 763 /* Tx and RX FIFO configuration */ 764 cr3 = readl_relaxed(port->membase + ofs->cr3); 765 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 766 if (stm32_port->fifoen) { 767 cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 768 cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 769 cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 770 } 771 772 if (cflag & CSTOPB) 773 cr2 |= USART_CR2_STOP_2B; 774 775 bits = stm32_usart_get_databits(termios); 776 stm32_port->rdr_mask = (BIT(bits) - 1); 777 778 if (cflag & PARENB) { 779 bits++; 780 cr1 |= USART_CR1_PCE; 781 } 782 783 /* 784 * Word length configuration: 785 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 786 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 787 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 788 * M0 and M1 already cleared by cr1 initialization. 789 */ 790 if (bits == 9) 791 cr1 |= USART_CR1_M0; 792 else if ((bits == 7) && cfg->has_7bits_data) 793 cr1 |= USART_CR1_M1; 794 else if (bits != 8) 795 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 796 , bits); 797 798 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 799 stm32_port->fifoen)) { 800 if (cflag & CSTOPB) 801 bits = bits + 3; /* 1 start bit + 2 stop bits */ 802 else 803 bits = bits + 2; /* 1 start bit + 1 stop bit */ 804 805 /* RX timeout irq to occur after last stop bit + bits */ 806 stm32_port->cr1_irq = USART_CR1_RTOIE; 807 writel_relaxed(bits, port->membase + ofs->rtor); 808 cr2 |= USART_CR2_RTOEN; 809 /* Not using dma, enable fifo threshold irq */ 810 if (!stm32_port->rx_ch) 811 stm32_port->cr3_irq = USART_CR3_RXFTIE; 812 } 813 814 cr1 |= stm32_port->cr1_irq; 815 cr3 |= stm32_port->cr3_irq; 816 817 if (cflag & PARODD) 818 cr1 |= USART_CR1_PS; 819 820 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 821 if (cflag & CRTSCTS) { 822 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 823 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 824 } 825 826 /* Handle modem control interrupts */ 827 if (UART_ENABLE_MS(port, termios->c_cflag)) 828 stm32_usart_enable_ms(port); 829 else 830 stm32_usart_disable_ms(port); 831 832 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 833 834 /* 835 * The USART supports 16 or 8 times oversampling. 836 * By default we prefer 16 times oversampling, so that the receiver 837 * has a better tolerance to clock deviations. 838 * 8 times oversampling is only used to achieve higher speeds. 839 */ 840 if (usartdiv < 16) { 841 oversampling = 8; 842 cr1 |= USART_CR1_OVER8; 843 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 844 } else { 845 oversampling = 16; 846 cr1 &= ~USART_CR1_OVER8; 847 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 848 } 849 850 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 851 fraction = usartdiv % oversampling; 852 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 853 854 uart_update_timeout(port, cflag, baud); 855 856 port->read_status_mask = USART_SR_ORE; 857 if (termios->c_iflag & INPCK) 858 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 859 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 860 port->read_status_mask |= USART_SR_FE; 861 862 /* Characters to ignore */ 863 port->ignore_status_mask = 0; 864 if (termios->c_iflag & IGNPAR) 865 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 866 if (termios->c_iflag & IGNBRK) { 867 port->ignore_status_mask |= USART_SR_FE; 868 /* 869 * If we're ignoring parity and break indicators, 870 * ignore overruns too (for real raw support). 871 */ 872 if (termios->c_iflag & IGNPAR) 873 port->ignore_status_mask |= USART_SR_ORE; 874 } 875 876 /* Ignore all characters if CREAD is not set */ 877 if ((termios->c_cflag & CREAD) == 0) 878 port->ignore_status_mask |= USART_SR_DUMMY_RX; 879 880 if (stm32_port->rx_ch) 881 cr3 |= USART_CR3_DMAR; 882 883 if (rs485conf->flags & SER_RS485_ENABLED) { 884 stm32_usart_config_reg_rs485(&cr1, &cr3, 885 rs485conf->delay_rts_before_send, 886 rs485conf->delay_rts_after_send, 887 baud); 888 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 889 cr3 &= ~USART_CR3_DEP; 890 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 891 } else { 892 cr3 |= USART_CR3_DEP; 893 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 894 } 895 896 } else { 897 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 898 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 899 } 900 901 writel_relaxed(cr3, port->membase + ofs->cr3); 902 writel_relaxed(cr2, port->membase + ofs->cr2); 903 writel_relaxed(cr1, port->membase + ofs->cr1); 904 905 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 906 spin_unlock_irqrestore(&port->lock, flags); 907 } 908 909 static const char *stm32_usart_type(struct uart_port *port) 910 { 911 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 912 } 913 914 static void stm32_usart_release_port(struct uart_port *port) 915 { 916 } 917 918 static int stm32_usart_request_port(struct uart_port *port) 919 { 920 return 0; 921 } 922 923 static void stm32_usart_config_port(struct uart_port *port, int flags) 924 { 925 if (flags & UART_CONFIG_TYPE) 926 port->type = PORT_STM32; 927 } 928 929 static int 930 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 931 { 932 /* No user changeable parameters */ 933 return -EINVAL; 934 } 935 936 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 937 unsigned int oldstate) 938 { 939 struct stm32_port *stm32port = container_of(port, 940 struct stm32_port, port); 941 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 942 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 943 unsigned long flags = 0; 944 945 switch (state) { 946 case UART_PM_STATE_ON: 947 pm_runtime_get_sync(port->dev); 948 break; 949 case UART_PM_STATE_OFF: 950 spin_lock_irqsave(&port->lock, flags); 951 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 952 spin_unlock_irqrestore(&port->lock, flags); 953 pm_runtime_put_sync(port->dev); 954 break; 955 } 956 } 957 958 static const struct uart_ops stm32_uart_ops = { 959 .tx_empty = stm32_usart_tx_empty, 960 .set_mctrl = stm32_usart_set_mctrl, 961 .get_mctrl = stm32_usart_get_mctrl, 962 .stop_tx = stm32_usart_stop_tx, 963 .start_tx = stm32_usart_start_tx, 964 .throttle = stm32_usart_throttle, 965 .unthrottle = stm32_usart_unthrottle, 966 .stop_rx = stm32_usart_stop_rx, 967 .enable_ms = stm32_usart_enable_ms, 968 .break_ctl = stm32_usart_break_ctl, 969 .startup = stm32_usart_startup, 970 .shutdown = stm32_usart_shutdown, 971 .set_termios = stm32_usart_set_termios, 972 .pm = stm32_usart_pm, 973 .type = stm32_usart_type, 974 .release_port = stm32_usart_release_port, 975 .request_port = stm32_usart_request_port, 976 .config_port = stm32_usart_config_port, 977 .verify_port = stm32_usart_verify_port, 978 }; 979 980 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 981 { 982 clk_disable_unprepare(stm32port->clk); 983 } 984 985 static int stm32_usart_init_port(struct stm32_port *stm32port, 986 struct platform_device *pdev) 987 { 988 struct uart_port *port = &stm32port->port; 989 struct resource *res; 990 int ret, irq; 991 992 irq = platform_get_irq(pdev, 0); 993 if (irq <= 0) 994 return irq ? : -ENODEV; 995 996 port->iotype = UPIO_MEM; 997 port->flags = UPF_BOOT_AUTOCONF; 998 port->ops = &stm32_uart_ops; 999 port->dev = &pdev->dev; 1000 port->fifosize = stm32port->info->cfg.fifosize; 1001 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1002 port->irq = irq; 1003 port->rs485_config = stm32_usart_config_rs485; 1004 1005 ret = stm32_usart_init_rs485(port, pdev); 1006 if (ret) 1007 return ret; 1008 1009 if (stm32port->info->cfg.has_wakeup) { 1010 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); 1011 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 1012 return stm32port->wakeirq ? : -ENODEV; 1013 } 1014 1015 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1016 1017 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1018 port->membase = devm_ioremap_resource(&pdev->dev, res); 1019 if (IS_ERR(port->membase)) 1020 return PTR_ERR(port->membase); 1021 port->mapbase = res->start; 1022 1023 spin_lock_init(&port->lock); 1024 1025 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1026 if (IS_ERR(stm32port->clk)) 1027 return PTR_ERR(stm32port->clk); 1028 1029 /* Ensure that clk rate is correct by enabling the clk */ 1030 ret = clk_prepare_enable(stm32port->clk); 1031 if (ret) 1032 return ret; 1033 1034 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1035 if (!stm32port->port.uartclk) { 1036 ret = -EINVAL; 1037 goto err_clk; 1038 } 1039 1040 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1041 if (IS_ERR(stm32port->gpios)) { 1042 ret = PTR_ERR(stm32port->gpios); 1043 goto err_clk; 1044 } 1045 1046 /* 1047 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1048 * properties should not be specified. 1049 */ 1050 if (stm32port->hw_flow_control) { 1051 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1052 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1053 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1054 ret = -EINVAL; 1055 goto err_clk; 1056 } 1057 } 1058 1059 return ret; 1060 1061 err_clk: 1062 clk_disable_unprepare(stm32port->clk); 1063 1064 return ret; 1065 } 1066 1067 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1068 { 1069 struct device_node *np = pdev->dev.of_node; 1070 int id; 1071 1072 if (!np) 1073 return NULL; 1074 1075 id = of_alias_get_id(np, "serial"); 1076 if (id < 0) { 1077 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1078 return NULL; 1079 } 1080 1081 if (WARN_ON(id >= STM32_MAX_PORTS)) 1082 return NULL; 1083 1084 stm32_ports[id].hw_flow_control = 1085 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1086 of_property_read_bool (np, "uart-has-rtscts"); 1087 stm32_ports[id].port.line = id; 1088 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1089 stm32_ports[id].cr3_irq = 0; 1090 stm32_ports[id].last_res = RX_BUF_L; 1091 return &stm32_ports[id]; 1092 } 1093 1094 #ifdef CONFIG_OF 1095 static const struct of_device_id stm32_match[] = { 1096 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1097 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1098 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1099 {}, 1100 }; 1101 1102 MODULE_DEVICE_TABLE(of, stm32_match); 1103 #endif 1104 1105 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1106 struct platform_device *pdev) 1107 { 1108 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1109 struct uart_port *port = &stm32port->port; 1110 struct device *dev = &pdev->dev; 1111 struct dma_slave_config config; 1112 struct dma_async_tx_descriptor *desc = NULL; 1113 int ret; 1114 1115 /* Request DMA RX channel */ 1116 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1117 if (!stm32port->rx_ch) { 1118 dev_info(dev, "rx dma alloc failed\n"); 1119 return -ENODEV; 1120 } 1121 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1122 &stm32port->rx_dma_buf, 1123 GFP_KERNEL); 1124 if (!stm32port->rx_buf) { 1125 ret = -ENOMEM; 1126 goto alloc_err; 1127 } 1128 1129 /* Configure DMA channel */ 1130 memset(&config, 0, sizeof(config)); 1131 config.src_addr = port->mapbase + ofs->rdr; 1132 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1133 1134 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1135 if (ret < 0) { 1136 dev_err(dev, "rx dma channel config failed\n"); 1137 ret = -ENODEV; 1138 goto config_err; 1139 } 1140 1141 /* Prepare a DMA cyclic transaction */ 1142 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1143 stm32port->rx_dma_buf, 1144 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1145 DMA_PREP_INTERRUPT); 1146 if (!desc) { 1147 dev_err(dev, "rx dma prep cyclic failed\n"); 1148 ret = -ENODEV; 1149 goto config_err; 1150 } 1151 1152 /* No callback as dma buffer is drained on usart interrupt */ 1153 desc->callback = NULL; 1154 desc->callback_param = NULL; 1155 1156 /* Push current DMA transaction in the pending queue */ 1157 ret = dma_submit_error(dmaengine_submit(desc)); 1158 if (ret) { 1159 dmaengine_terminate_sync(stm32port->rx_ch); 1160 goto config_err; 1161 } 1162 1163 /* Issue pending DMA requests */ 1164 dma_async_issue_pending(stm32port->rx_ch); 1165 1166 return 0; 1167 1168 config_err: 1169 dma_free_coherent(&pdev->dev, 1170 RX_BUF_L, stm32port->rx_buf, 1171 stm32port->rx_dma_buf); 1172 1173 alloc_err: 1174 dma_release_channel(stm32port->rx_ch); 1175 stm32port->rx_ch = NULL; 1176 1177 return ret; 1178 } 1179 1180 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1181 struct platform_device *pdev) 1182 { 1183 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1184 struct uart_port *port = &stm32port->port; 1185 struct device *dev = &pdev->dev; 1186 struct dma_slave_config config; 1187 int ret; 1188 1189 stm32port->tx_dma_busy = false; 1190 1191 /* Request DMA TX channel */ 1192 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1193 if (!stm32port->tx_ch) { 1194 dev_info(dev, "tx dma alloc failed\n"); 1195 return -ENODEV; 1196 } 1197 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1198 &stm32port->tx_dma_buf, 1199 GFP_KERNEL); 1200 if (!stm32port->tx_buf) { 1201 ret = -ENOMEM; 1202 goto alloc_err; 1203 } 1204 1205 /* Configure DMA channel */ 1206 memset(&config, 0, sizeof(config)); 1207 config.dst_addr = port->mapbase + ofs->tdr; 1208 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1209 1210 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1211 if (ret < 0) { 1212 dev_err(dev, "tx dma channel config failed\n"); 1213 ret = -ENODEV; 1214 goto config_err; 1215 } 1216 1217 return 0; 1218 1219 config_err: 1220 dma_free_coherent(&pdev->dev, 1221 TX_BUF_L, stm32port->tx_buf, 1222 stm32port->tx_dma_buf); 1223 1224 alloc_err: 1225 dma_release_channel(stm32port->tx_ch); 1226 stm32port->tx_ch = NULL; 1227 1228 return ret; 1229 } 1230 1231 static int stm32_usart_serial_probe(struct platform_device *pdev) 1232 { 1233 struct stm32_port *stm32port; 1234 int ret; 1235 1236 stm32port = stm32_usart_of_get_port(pdev); 1237 if (!stm32port) 1238 return -ENODEV; 1239 1240 stm32port->info = of_device_get_match_data(&pdev->dev); 1241 if (!stm32port->info) 1242 return -EINVAL; 1243 1244 ret = stm32_usart_init_port(stm32port, pdev); 1245 if (ret) 1246 return ret; 1247 1248 if (stm32port->wakeirq > 0) { 1249 ret = device_init_wakeup(&pdev->dev, true); 1250 if (ret) 1251 goto err_uninit; 1252 1253 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1254 stm32port->wakeirq); 1255 if (ret) 1256 goto err_nowup; 1257 1258 device_set_wakeup_enable(&pdev->dev, false); 1259 } 1260 1261 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1262 if (ret) 1263 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1264 1265 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1266 if (ret) 1267 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1268 1269 platform_set_drvdata(pdev, &stm32port->port); 1270 1271 pm_runtime_get_noresume(&pdev->dev); 1272 pm_runtime_set_active(&pdev->dev); 1273 pm_runtime_enable(&pdev->dev); 1274 1275 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1276 if (ret) 1277 goto err_port; 1278 1279 pm_runtime_put_sync(&pdev->dev); 1280 1281 return 0; 1282 1283 err_port: 1284 pm_runtime_disable(&pdev->dev); 1285 pm_runtime_set_suspended(&pdev->dev); 1286 pm_runtime_put_noidle(&pdev->dev); 1287 1288 if (stm32port->rx_ch) { 1289 dmaengine_terminate_async(stm32port->rx_ch); 1290 dma_release_channel(stm32port->rx_ch); 1291 } 1292 1293 if (stm32port->rx_dma_buf) 1294 dma_free_coherent(&pdev->dev, 1295 RX_BUF_L, stm32port->rx_buf, 1296 stm32port->rx_dma_buf); 1297 1298 if (stm32port->tx_ch) { 1299 dmaengine_terminate_async(stm32port->tx_ch); 1300 dma_release_channel(stm32port->tx_ch); 1301 } 1302 1303 if (stm32port->tx_dma_buf) 1304 dma_free_coherent(&pdev->dev, 1305 TX_BUF_L, stm32port->tx_buf, 1306 stm32port->tx_dma_buf); 1307 1308 if (stm32port->wakeirq > 0) 1309 dev_pm_clear_wake_irq(&pdev->dev); 1310 1311 err_nowup: 1312 if (stm32port->wakeirq > 0) 1313 device_init_wakeup(&pdev->dev, false); 1314 1315 err_uninit: 1316 stm32_usart_deinit_port(stm32port); 1317 1318 return ret; 1319 } 1320 1321 static int stm32_usart_serial_remove(struct platform_device *pdev) 1322 { 1323 struct uart_port *port = platform_get_drvdata(pdev); 1324 struct stm32_port *stm32_port = to_stm32_port(port); 1325 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1326 int err; 1327 1328 pm_runtime_get_sync(&pdev->dev); 1329 err = uart_remove_one_port(&stm32_usart_driver, port); 1330 if (err) 1331 return(err); 1332 1333 pm_runtime_disable(&pdev->dev); 1334 pm_runtime_set_suspended(&pdev->dev); 1335 pm_runtime_put_noidle(&pdev->dev); 1336 1337 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1338 1339 if (stm32_port->rx_ch) { 1340 dmaengine_terminate_async(stm32_port->rx_ch); 1341 dma_release_channel(stm32_port->rx_ch); 1342 } 1343 1344 if (stm32_port->rx_dma_buf) 1345 dma_free_coherent(&pdev->dev, 1346 RX_BUF_L, stm32_port->rx_buf, 1347 stm32_port->rx_dma_buf); 1348 1349 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1350 1351 if (stm32_port->tx_ch) { 1352 dmaengine_terminate_async(stm32_port->tx_ch); 1353 dma_release_channel(stm32_port->tx_ch); 1354 } 1355 1356 if (stm32_port->tx_dma_buf) 1357 dma_free_coherent(&pdev->dev, 1358 TX_BUF_L, stm32_port->tx_buf, 1359 stm32_port->tx_dma_buf); 1360 1361 if (stm32_port->wakeirq > 0) { 1362 dev_pm_clear_wake_irq(&pdev->dev); 1363 device_init_wakeup(&pdev->dev, false); 1364 } 1365 1366 stm32_usart_deinit_port(stm32_port); 1367 1368 return 0; 1369 } 1370 1371 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1372 static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1373 { 1374 struct stm32_port *stm32_port = to_stm32_port(port); 1375 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1376 1377 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1378 cpu_relax(); 1379 1380 writel_relaxed(ch, port->membase + ofs->tdr); 1381 } 1382 1383 static void stm32_usart_console_write(struct console *co, const char *s, 1384 unsigned int cnt) 1385 { 1386 struct uart_port *port = &stm32_ports[co->index].port; 1387 struct stm32_port *stm32_port = to_stm32_port(port); 1388 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1389 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1390 unsigned long flags; 1391 u32 old_cr1, new_cr1; 1392 int locked = 1; 1393 1394 local_irq_save(flags); 1395 if (port->sysrq) 1396 locked = 0; 1397 else if (oops_in_progress) 1398 locked = spin_trylock(&port->lock); 1399 else 1400 spin_lock(&port->lock); 1401 1402 /* Save and disable interrupts, enable the transmitter */ 1403 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1404 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1405 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1406 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1407 1408 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1409 1410 /* Restore interrupt state */ 1411 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1412 1413 if (locked) 1414 spin_unlock(&port->lock); 1415 local_irq_restore(flags); 1416 } 1417 1418 static int stm32_usart_console_setup(struct console *co, char *options) 1419 { 1420 struct stm32_port *stm32port; 1421 int baud = 9600; 1422 int bits = 8; 1423 int parity = 'n'; 1424 int flow = 'n'; 1425 1426 if (co->index >= STM32_MAX_PORTS) 1427 return -ENODEV; 1428 1429 stm32port = &stm32_ports[co->index]; 1430 1431 /* 1432 * This driver does not support early console initialization 1433 * (use ARM early printk support instead), so we only expect 1434 * this to be called during the uart port registration when the 1435 * driver gets probed and the port should be mapped at that point. 1436 */ 1437 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1438 return -ENXIO; 1439 1440 if (options) 1441 uart_parse_options(options, &baud, &parity, &bits, &flow); 1442 1443 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1444 } 1445 1446 static struct console stm32_console = { 1447 .name = STM32_SERIAL_NAME, 1448 .device = uart_console_device, 1449 .write = stm32_usart_console_write, 1450 .setup = stm32_usart_console_setup, 1451 .flags = CON_PRINTBUFFER, 1452 .index = -1, 1453 .data = &stm32_usart_driver, 1454 }; 1455 1456 #define STM32_SERIAL_CONSOLE (&stm32_console) 1457 1458 #else 1459 #define STM32_SERIAL_CONSOLE NULL 1460 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1461 1462 static struct uart_driver stm32_usart_driver = { 1463 .driver_name = DRIVER_NAME, 1464 .dev_name = STM32_SERIAL_NAME, 1465 .major = 0, 1466 .minor = 0, 1467 .nr = STM32_MAX_PORTS, 1468 .cons = STM32_SERIAL_CONSOLE, 1469 }; 1470 1471 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1472 bool enable) 1473 { 1474 struct stm32_port *stm32_port = to_stm32_port(port); 1475 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1476 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1477 u32 val; 1478 1479 if (stm32_port->wakeirq <= 0) 1480 return; 1481 1482 if (enable) { 1483 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1484 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1485 val = readl_relaxed(port->membase + ofs->cr3); 1486 val &= ~USART_CR3_WUS_MASK; 1487 /* Enable Wake up interrupt from low power on start bit */ 1488 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1489 writel_relaxed(val, port->membase + ofs->cr3); 1490 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1491 } else { 1492 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1493 } 1494 } 1495 1496 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1497 { 1498 struct uart_port *port = dev_get_drvdata(dev); 1499 1500 uart_suspend_port(&stm32_usart_driver, port); 1501 1502 if (device_may_wakeup(dev)) 1503 stm32_usart_serial_en_wakeup(port, true); 1504 else 1505 stm32_usart_serial_en_wakeup(port, false); 1506 1507 /* 1508 * When "no_console_suspend" is enabled, keep the pinctrl default state 1509 * and rely on bootloader stage to restore this state upon resume. 1510 * Otherwise, apply the idle or sleep states depending on wakeup 1511 * capabilities. 1512 */ 1513 if (console_suspend_enabled || !uart_console(port)) { 1514 if (device_may_wakeup(dev)) 1515 pinctrl_pm_select_idle_state(dev); 1516 else 1517 pinctrl_pm_select_sleep_state(dev); 1518 } 1519 1520 return 0; 1521 } 1522 1523 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1524 { 1525 struct uart_port *port = dev_get_drvdata(dev); 1526 1527 pinctrl_pm_select_default_state(dev); 1528 1529 if (device_may_wakeup(dev)) 1530 stm32_usart_serial_en_wakeup(port, false); 1531 1532 return uart_resume_port(&stm32_usart_driver, port); 1533 } 1534 1535 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1536 { 1537 struct uart_port *port = dev_get_drvdata(dev); 1538 struct stm32_port *stm32port = container_of(port, 1539 struct stm32_port, port); 1540 1541 clk_disable_unprepare(stm32port->clk); 1542 1543 return 0; 1544 } 1545 1546 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1547 { 1548 struct uart_port *port = dev_get_drvdata(dev); 1549 struct stm32_port *stm32port = container_of(port, 1550 struct stm32_port, port); 1551 1552 return clk_prepare_enable(stm32port->clk); 1553 } 1554 1555 static const struct dev_pm_ops stm32_serial_pm_ops = { 1556 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1557 stm32_usart_runtime_resume, NULL) 1558 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1559 stm32_usart_serial_resume) 1560 }; 1561 1562 static struct platform_driver stm32_serial_driver = { 1563 .probe = stm32_usart_serial_probe, 1564 .remove = stm32_usart_serial_remove, 1565 .driver = { 1566 .name = DRIVER_NAME, 1567 .pm = &stm32_serial_pm_ops, 1568 .of_match_table = of_match_ptr(stm32_match), 1569 }, 1570 }; 1571 1572 static int __init stm32_usart_init(void) 1573 { 1574 static char banner[] __initdata = "STM32 USART driver initialized"; 1575 int ret; 1576 1577 pr_info("%s\n", banner); 1578 1579 ret = uart_register_driver(&stm32_usart_driver); 1580 if (ret) 1581 return ret; 1582 1583 ret = platform_driver_register(&stm32_serial_driver); 1584 if (ret) 1585 uart_unregister_driver(&stm32_usart_driver); 1586 1587 return ret; 1588 } 1589 1590 static void __exit stm32_usart_exit(void) 1591 { 1592 platform_driver_unregister(&stm32_serial_driver); 1593 uart_unregister_driver(&stm32_usart_driver); 1594 } 1595 1596 module_init(stm32_usart_init); 1597 module_exit(stm32_usart_exit); 1598 1599 MODULE_ALIAS("platform:" DRIVER_NAME); 1600 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1601 MODULE_LICENSE("GPL v2"); 1602