1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald.baeza@foss.st.com> 7 * Erwan Le Ray <erwan.leray@foss.st.com> 8 * 9 * Inspired by st-asc.c from STMicroelectronics (c) 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/delay.h> 15 #include <linux/dma-direction.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/irq.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/spinlock.h> 31 #include <linux/sysrq.h> 32 #include <linux/tty_flip.h> 33 #include <linux/tty.h> 34 35 #include "serial_mctrl_gpio.h" 36 #include "stm32-usart.h" 37 38 static void stm32_usart_stop_tx(struct uart_port *port); 39 static void stm32_usart_transmit_chars(struct uart_port *port); 40 41 static inline struct stm32_port *to_stm32_port(struct uart_port *port) 42 { 43 return container_of(port, struct stm32_port, port); 44 } 45 46 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits) 47 { 48 u32 val; 49 50 val = readl_relaxed(port->membase + reg); 51 val |= bits; 52 writel_relaxed(val, port->membase + reg); 53 } 54 55 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits) 56 { 57 u32 val; 58 59 val = readl_relaxed(port->membase + reg); 60 val &= ~bits; 61 writel_relaxed(val, port->membase + reg); 62 } 63 64 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, 65 u32 delay_DDE, u32 baud) 66 { 67 u32 rs485_deat_dedt; 68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT); 69 bool over8; 70 71 *cr3 |= USART_CR3_DEM; 72 over8 = *cr1 & USART_CR1_OVER8; 73 74 if (over8) 75 rs485_deat_dedt = delay_ADE * baud * 8; 76 else 77 rs485_deat_dedt = delay_ADE * baud * 16; 78 79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 81 rs485_deat_dedt_max : rs485_deat_dedt; 82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) & 83 USART_CR1_DEAT_MASK; 84 *cr1 |= rs485_deat_dedt; 85 86 if (over8) 87 rs485_deat_dedt = delay_DDE * baud * 8; 88 else 89 rs485_deat_dedt = delay_DDE * baud * 16; 90 91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000); 92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ? 93 rs485_deat_dedt_max : rs485_deat_dedt; 94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) & 95 USART_CR1_DEDT_MASK; 96 *cr1 |= rs485_deat_dedt; 97 } 98 99 static int stm32_usart_config_rs485(struct uart_port *port, 100 struct serial_rs485 *rs485conf) 101 { 102 struct stm32_port *stm32_port = to_stm32_port(port); 103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 105 u32 usartdiv, baud, cr1, cr3; 106 bool over8; 107 108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 109 110 port->rs485 = *rs485conf; 111 112 rs485conf->flags |= SER_RS485_RX_DURING_TX; 113 114 if (rs485conf->flags & SER_RS485_ENABLED) { 115 cr1 = readl_relaxed(port->membase + ofs->cr1); 116 cr3 = readl_relaxed(port->membase + ofs->cr3); 117 usartdiv = readl_relaxed(port->membase + ofs->brr); 118 usartdiv = usartdiv & GENMASK(15, 0); 119 over8 = cr1 & USART_CR1_OVER8; 120 121 if (over8) 122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0)) 123 << USART_BRR_04_R_SHIFT; 124 125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); 126 stm32_usart_config_reg_rs485(&cr1, &cr3, 127 rs485conf->delay_rts_before_send, 128 rs485conf->delay_rts_after_send, 129 baud); 130 131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 132 cr3 &= ~USART_CR3_DEP; 133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 134 } else { 135 cr3 |= USART_CR3_DEP; 136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 137 } 138 139 writel_relaxed(cr3, port->membase + ofs->cr3); 140 writel_relaxed(cr1, port->membase + ofs->cr1); 141 } else { 142 stm32_usart_clr_bits(port, ofs->cr3, 143 USART_CR3_DEM | USART_CR3_DEP); 144 stm32_usart_clr_bits(port, ofs->cr1, 145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 146 } 147 148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 149 150 return 0; 151 } 152 153 static int stm32_usart_init_rs485(struct uart_port *port, 154 struct platform_device *pdev) 155 { 156 struct serial_rs485 *rs485conf = &port->rs485; 157 158 rs485conf->flags = 0; 159 rs485conf->delay_rts_before_send = 0; 160 rs485conf->delay_rts_after_send = 0; 161 162 if (!pdev->dev.of_node) 163 return -ENODEV; 164 165 return uart_get_rs485_mode(port); 166 } 167 168 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr, 169 int *last_res, bool threaded) 170 { 171 struct stm32_port *stm32_port = to_stm32_port(port); 172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 173 enum dma_status status; 174 struct dma_tx_state state; 175 176 *sr = readl_relaxed(port->membase + ofs->isr); 177 178 if (threaded && stm32_port->rx_ch) { 179 status = dmaengine_tx_status(stm32_port->rx_ch, 180 stm32_port->rx_ch->cookie, 181 &state); 182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue)) 183 return 1; 184 else 185 return 0; 186 } else if (*sr & USART_SR_RXNE) { 187 return 1; 188 } 189 return 0; 190 } 191 192 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr, 193 int *last_res) 194 { 195 struct stm32_port *stm32_port = to_stm32_port(port); 196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 197 unsigned long c; 198 199 if (stm32_port->rx_ch) { 200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; 201 if ((*last_res) == 0) 202 *last_res = RX_BUF_L; 203 } else { 204 c = readl_relaxed(port->membase + ofs->rdr); 205 /* apply RDR data mask */ 206 c &= stm32_port->rdr_mask; 207 } 208 209 return c; 210 } 211 212 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded) 213 { 214 struct tty_port *tport = &port->state->port; 215 struct stm32_port *stm32_port = to_stm32_port(port); 216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 217 unsigned long c, flags; 218 u32 sr; 219 char flag; 220 221 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) 222 pm_wakeup_event(tport->tty->dev, 0); 223 224 if (threaded) 225 spin_lock_irqsave(&port->lock, flags); 226 else 227 spin_lock(&port->lock); 228 229 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, 230 threaded)) { 231 sr |= USART_SR_DUMMY_RX; 232 flag = TTY_NORMAL; 233 234 /* 235 * Status bits has to be cleared before reading the RDR: 236 * In FIFO mode, reading the RDR will pop the next data 237 * (if any) along with its status bits into the SR. 238 * Not doing so leads to misalignement between RDR and SR, 239 * and clear status bits of the next rx data. 240 * 241 * Clear errors flags for stm32f7 and stm32h7 compatible 242 * devices. On stm32f4 compatible devices, the error bit is 243 * cleared by the sequence [read SR - read DR]. 244 */ 245 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) 246 writel_relaxed(sr & USART_SR_ERR_MASK, 247 port->membase + ofs->icr); 248 249 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); 250 port->icount.rx++; 251 if (sr & USART_SR_ERR_MASK) { 252 if (sr & USART_SR_ORE) { 253 port->icount.overrun++; 254 } else if (sr & USART_SR_PE) { 255 port->icount.parity++; 256 } else if (sr & USART_SR_FE) { 257 /* Break detection if character is null */ 258 if (!c) { 259 port->icount.brk++; 260 if (uart_handle_break(port)) 261 continue; 262 } else { 263 port->icount.frame++; 264 } 265 } 266 267 sr &= port->read_status_mask; 268 269 if (sr & USART_SR_PE) { 270 flag = TTY_PARITY; 271 } else if (sr & USART_SR_FE) { 272 if (!c) 273 flag = TTY_BREAK; 274 else 275 flag = TTY_FRAME; 276 } 277 } 278 279 if (uart_handle_sysrq_char(port, c)) 280 continue; 281 uart_insert_char(port, sr, USART_SR_ORE, c, flag); 282 } 283 284 if (threaded) 285 spin_unlock_irqrestore(&port->lock, flags); 286 else 287 spin_unlock(&port->lock); 288 289 tty_flip_buffer_push(tport); 290 } 291 292 static void stm32_usart_tx_dma_complete(void *arg) 293 { 294 struct uart_port *port = arg; 295 struct stm32_port *stm32port = to_stm32_port(port); 296 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 297 298 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 299 stm32port->tx_dma_busy = false; 300 301 /* Let's see if we have pending data to send */ 302 stm32_usart_transmit_chars(port); 303 } 304 305 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) 306 { 307 struct stm32_port *stm32_port = to_stm32_port(port); 308 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 309 310 /* 311 * Enables TX FIFO threashold irq when FIFO is enabled, 312 * or TX empty irq when FIFO is disabled 313 */ 314 if (stm32_port->fifoen) 315 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); 316 else 317 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); 318 } 319 320 static void stm32_usart_tx_interrupt_disable(struct uart_port *port) 321 { 322 struct stm32_port *stm32_port = to_stm32_port(port); 323 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 324 325 if (stm32_port->fifoen) 326 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); 327 else 328 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); 329 } 330 331 static void stm32_usart_transmit_chars_pio(struct uart_port *port) 332 { 333 struct stm32_port *stm32_port = to_stm32_port(port); 334 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 335 struct circ_buf *xmit = &port->state->xmit; 336 337 if (stm32_port->tx_dma_busy) { 338 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 339 stm32_port->tx_dma_busy = false; 340 } 341 342 while (!uart_circ_empty(xmit)) { 343 /* Check that TDR is empty before filling FIFO */ 344 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 345 break; 346 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); 347 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 348 port->icount.tx++; 349 } 350 351 /* rely on TXE irq (mask or unmask) for sending remaining data */ 352 if (uart_circ_empty(xmit)) 353 stm32_usart_tx_interrupt_disable(port); 354 else 355 stm32_usart_tx_interrupt_enable(port); 356 } 357 358 static void stm32_usart_transmit_chars_dma(struct uart_port *port) 359 { 360 struct stm32_port *stm32port = to_stm32_port(port); 361 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 362 struct circ_buf *xmit = &port->state->xmit; 363 struct dma_async_tx_descriptor *desc = NULL; 364 unsigned int count, i; 365 366 if (stm32port->tx_dma_busy) 367 return; 368 369 stm32port->tx_dma_busy = true; 370 371 count = uart_circ_chars_pending(xmit); 372 373 if (count > TX_BUF_L) 374 count = TX_BUF_L; 375 376 if (xmit->tail < xmit->head) { 377 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); 378 } else { 379 size_t one = UART_XMIT_SIZE - xmit->tail; 380 size_t two; 381 382 if (one > count) 383 one = count; 384 two = count - one; 385 386 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); 387 if (two) 388 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); 389 } 390 391 desc = dmaengine_prep_slave_single(stm32port->tx_ch, 392 stm32port->tx_dma_buf, 393 count, 394 DMA_MEM_TO_DEV, 395 DMA_PREP_INTERRUPT); 396 397 if (!desc) 398 goto fallback_err; 399 400 desc->callback = stm32_usart_tx_dma_complete; 401 desc->callback_param = port; 402 403 /* Push current DMA TX transaction in the pending queue */ 404 if (dma_submit_error(dmaengine_submit(desc))) { 405 /* dma no yet started, safe to free resources */ 406 dmaengine_terminate_async(stm32port->tx_ch); 407 goto fallback_err; 408 } 409 410 /* Issue pending DMA TX requests */ 411 dma_async_issue_pending(stm32port->tx_ch); 412 413 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 414 415 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 416 port->icount.tx += count; 417 return; 418 419 fallback_err: 420 for (i = count; i > 0; i--) 421 stm32_usart_transmit_chars_pio(port); 422 } 423 424 static void stm32_usart_transmit_chars(struct uart_port *port) 425 { 426 struct stm32_port *stm32_port = to_stm32_port(port); 427 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 428 struct circ_buf *xmit = &port->state->xmit; 429 430 if (port->x_char) { 431 if (stm32_port->tx_dma_busy) 432 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 433 writel_relaxed(port->x_char, port->membase + ofs->tdr); 434 port->x_char = 0; 435 port->icount.tx++; 436 if (stm32_port->tx_dma_busy) 437 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); 438 return; 439 } 440 441 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 442 stm32_usart_tx_interrupt_disable(port); 443 return; 444 } 445 446 if (ofs->icr == UNDEF_REG) 447 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); 448 else 449 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); 450 451 if (stm32_port->tx_ch) 452 stm32_usart_transmit_chars_dma(port); 453 else 454 stm32_usart_transmit_chars_pio(port); 455 456 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 457 uart_write_wakeup(port); 458 459 if (uart_circ_empty(xmit)) 460 stm32_usart_tx_interrupt_disable(port); 461 } 462 463 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr) 464 { 465 struct uart_port *port = ptr; 466 struct stm32_port *stm32_port = to_stm32_port(port); 467 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 468 u32 sr; 469 470 sr = readl_relaxed(port->membase + ofs->isr); 471 472 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) 473 writel_relaxed(USART_ICR_RTOCF, 474 port->membase + ofs->icr); 475 476 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) 477 writel_relaxed(USART_ICR_WUCF, 478 port->membase + ofs->icr); 479 480 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) 481 stm32_usart_receive_chars(port, false); 482 483 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 484 spin_lock(&port->lock); 485 stm32_usart_transmit_chars(port); 486 spin_unlock(&port->lock); 487 } 488 489 if (stm32_port->rx_ch) 490 return IRQ_WAKE_THREAD; 491 else 492 return IRQ_HANDLED; 493 } 494 495 static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr) 496 { 497 struct uart_port *port = ptr; 498 struct stm32_port *stm32_port = to_stm32_port(port); 499 500 if (stm32_port->rx_ch) 501 stm32_usart_receive_chars(port, true); 502 503 return IRQ_HANDLED; 504 } 505 506 static unsigned int stm32_usart_tx_empty(struct uart_port *port) 507 { 508 struct stm32_port *stm32_port = to_stm32_port(port); 509 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 510 511 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; 512 } 513 514 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl) 515 { 516 struct stm32_port *stm32_port = to_stm32_port(port); 517 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 518 519 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 520 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); 521 else 522 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); 523 524 mctrl_gpio_set(stm32_port->gpios, mctrl); 525 } 526 527 static unsigned int stm32_usart_get_mctrl(struct uart_port *port) 528 { 529 struct stm32_port *stm32_port = to_stm32_port(port); 530 unsigned int ret; 531 532 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ 533 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 534 535 return mctrl_gpio_get(stm32_port->gpios, &ret); 536 } 537 538 static void stm32_usart_enable_ms(struct uart_port *port) 539 { 540 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); 541 } 542 543 static void stm32_usart_disable_ms(struct uart_port *port) 544 { 545 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); 546 } 547 548 /* Transmit stop */ 549 static void stm32_usart_stop_tx(struct uart_port *port) 550 { 551 struct stm32_port *stm32_port = to_stm32_port(port); 552 struct serial_rs485 *rs485conf = &port->rs485; 553 554 stm32_usart_tx_interrupt_disable(port); 555 556 if (rs485conf->flags & SER_RS485_ENABLED) { 557 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 558 mctrl_gpio_set(stm32_port->gpios, 559 stm32_port->port.mctrl & ~TIOCM_RTS); 560 } else { 561 mctrl_gpio_set(stm32_port->gpios, 562 stm32_port->port.mctrl | TIOCM_RTS); 563 } 564 } 565 } 566 567 /* There are probably characters waiting to be transmitted. */ 568 static void stm32_usart_start_tx(struct uart_port *port) 569 { 570 struct stm32_port *stm32_port = to_stm32_port(port); 571 struct serial_rs485 *rs485conf = &port->rs485; 572 struct circ_buf *xmit = &port->state->xmit; 573 574 if (uart_circ_empty(xmit)) 575 return; 576 577 if (rs485conf->flags & SER_RS485_ENABLED) { 578 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 579 mctrl_gpio_set(stm32_port->gpios, 580 stm32_port->port.mctrl | TIOCM_RTS); 581 } else { 582 mctrl_gpio_set(stm32_port->gpios, 583 stm32_port->port.mctrl & ~TIOCM_RTS); 584 } 585 } 586 587 stm32_usart_transmit_chars(port); 588 } 589 590 /* Throttle the remote when input buffer is about to overflow. */ 591 static void stm32_usart_throttle(struct uart_port *port) 592 { 593 struct stm32_port *stm32_port = to_stm32_port(port); 594 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 595 unsigned long flags; 596 597 spin_lock_irqsave(&port->lock, flags); 598 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 599 if (stm32_port->cr3_irq) 600 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 601 602 spin_unlock_irqrestore(&port->lock, flags); 603 } 604 605 /* Unthrottle the remote, the input buffer can now accept data. */ 606 static void stm32_usart_unthrottle(struct uart_port *port) 607 { 608 struct stm32_port *stm32_port = to_stm32_port(port); 609 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 610 unsigned long flags; 611 612 spin_lock_irqsave(&port->lock, flags); 613 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 614 if (stm32_port->cr3_irq) 615 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); 616 617 spin_unlock_irqrestore(&port->lock, flags); 618 } 619 620 /* Receive stop */ 621 static void stm32_usart_stop_rx(struct uart_port *port) 622 { 623 struct stm32_port *stm32_port = to_stm32_port(port); 624 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 625 626 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); 627 if (stm32_port->cr3_irq) 628 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 629 } 630 631 /* Handle breaks - ignored by us */ 632 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 633 { 634 } 635 636 static int stm32_usart_startup(struct uart_port *port) 637 { 638 struct stm32_port *stm32_port = to_stm32_port(port); 639 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 640 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 641 const char *name = to_platform_device(port->dev)->name; 642 u32 val; 643 int ret; 644 645 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, 646 stm32_usart_threaded_interrupt, 647 IRQF_NO_SUSPEND, name, port); 648 if (ret) 649 return ret; 650 651 /* RX FIFO Flush */ 652 if (ofs->rqr != UNDEF_REG) 653 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); 654 655 /* RX enabling */ 656 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); 657 stm32_usart_set_bits(port, ofs->cr1, val); 658 659 return 0; 660 } 661 662 static void stm32_usart_shutdown(struct uart_port *port) 663 { 664 struct stm32_port *stm32_port = to_stm32_port(port); 665 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 666 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 667 u32 val, isr; 668 int ret; 669 670 /* Disable modem control interrupts */ 671 stm32_usart_disable_ms(port); 672 673 val = USART_CR1_TXEIE | USART_CR1_TE; 674 val |= stm32_port->cr1_irq | USART_CR1_RE; 675 val |= BIT(cfg->uart_enable_bit); 676 if (stm32_port->fifoen) 677 val |= USART_CR1_FIFOEN; 678 679 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, 680 isr, (isr & USART_SR_TC), 681 10, 100000); 682 683 /* Send the TC error message only when ISR_TC is not set */ 684 if (ret) 685 dev_err(port->dev, "Transmission is not complete\n"); 686 687 stm32_usart_clr_bits(port, ofs->cr1, val); 688 689 free_irq(port->irq, port); 690 } 691 692 static unsigned int stm32_usart_get_databits(struct ktermios *termios) 693 { 694 unsigned int bits; 695 696 tcflag_t cflag = termios->c_cflag; 697 698 switch (cflag & CSIZE) { 699 /* 700 * CSIZE settings are not necessarily supported in hardware. 701 * CSIZE unsupported configurations are handled here to set word length 702 * to 8 bits word as default configuration and to print debug message. 703 */ 704 case CS5: 705 bits = 5; 706 break; 707 case CS6: 708 bits = 6; 709 break; 710 case CS7: 711 bits = 7; 712 break; 713 /* default including CS8 */ 714 default: 715 bits = 8; 716 break; 717 } 718 719 return bits; 720 } 721 722 static void stm32_usart_set_termios(struct uart_port *port, 723 struct ktermios *termios, 724 struct ktermios *old) 725 { 726 struct stm32_port *stm32_port = to_stm32_port(port); 727 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 728 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 729 struct serial_rs485 *rs485conf = &port->rs485; 730 unsigned int baud, bits; 731 u32 usartdiv, mantissa, fraction, oversampling; 732 tcflag_t cflag = termios->c_cflag; 733 u32 cr1, cr2, cr3, isr; 734 unsigned long flags; 735 int ret; 736 737 if (!stm32_port->hw_flow_control) 738 cflag &= ~CRTSCTS; 739 740 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 741 742 spin_lock_irqsave(&port->lock, flags); 743 744 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 745 isr, 746 (isr & USART_SR_TC), 747 10, 100000); 748 749 /* Send the TC error message only when ISR_TC is not set. */ 750 if (ret) 751 dev_err(port->dev, "Transmission is not complete\n"); 752 753 /* Stop serial port and reset value */ 754 writel_relaxed(0, port->membase + ofs->cr1); 755 756 /* flush RX & TX FIFO */ 757 if (ofs->rqr != UNDEF_REG) 758 stm32_usart_set_bits(port, ofs->rqr, 759 USART_RQR_TXFRQ | USART_RQR_RXFRQ); 760 761 cr1 = USART_CR1_TE | USART_CR1_RE; 762 if (stm32_port->fifoen) 763 cr1 |= USART_CR1_FIFOEN; 764 cr2 = 0; 765 766 /* Tx and RX FIFO configuration */ 767 cr3 = readl_relaxed(port->membase + ofs->cr3); 768 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE; 769 if (stm32_port->fifoen) { 770 cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); 771 cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; 772 cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; 773 } 774 775 if (cflag & CSTOPB) 776 cr2 |= USART_CR2_STOP_2B; 777 778 bits = stm32_usart_get_databits(termios); 779 stm32_port->rdr_mask = (BIT(bits) - 1); 780 781 if (cflag & PARENB) { 782 bits++; 783 cr1 |= USART_CR1_PCE; 784 } 785 786 /* 787 * Word length configuration: 788 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 789 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 790 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 791 * M0 and M1 already cleared by cr1 initialization. 792 */ 793 if (bits == 9) 794 cr1 |= USART_CR1_M0; 795 else if ((bits == 7) && cfg->has_7bits_data) 796 cr1 |= USART_CR1_M1; 797 else if (bits != 8) 798 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" 799 , bits); 800 801 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || 802 stm32_port->fifoen)) { 803 if (cflag & CSTOPB) 804 bits = bits + 3; /* 1 start bit + 2 stop bits */ 805 else 806 bits = bits + 2; /* 1 start bit + 1 stop bit */ 807 808 /* RX timeout irq to occur after last stop bit + bits */ 809 stm32_port->cr1_irq = USART_CR1_RTOIE; 810 writel_relaxed(bits, port->membase + ofs->rtor); 811 cr2 |= USART_CR2_RTOEN; 812 /* Not using dma, enable fifo threshold irq */ 813 if (!stm32_port->rx_ch) 814 stm32_port->cr3_irq = USART_CR3_RXFTIE; 815 } 816 817 cr1 |= stm32_port->cr1_irq; 818 cr3 |= stm32_port->cr3_irq; 819 820 if (cflag & PARODD) 821 cr1 |= USART_CR1_PS; 822 823 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 824 if (cflag & CRTSCTS) { 825 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 826 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE; 827 } 828 829 /* Handle modem control interrupts */ 830 if (UART_ENABLE_MS(port, termios->c_cflag)) 831 stm32_usart_enable_ms(port); 832 else 833 stm32_usart_disable_ms(port); 834 835 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 836 837 /* 838 * The USART supports 16 or 8 times oversampling. 839 * By default we prefer 16 times oversampling, so that the receiver 840 * has a better tolerance to clock deviations. 841 * 8 times oversampling is only used to achieve higher speeds. 842 */ 843 if (usartdiv < 16) { 844 oversampling = 8; 845 cr1 |= USART_CR1_OVER8; 846 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); 847 } else { 848 oversampling = 16; 849 cr1 &= ~USART_CR1_OVER8; 850 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); 851 } 852 853 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT; 854 fraction = usartdiv % oversampling; 855 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); 856 857 uart_update_timeout(port, cflag, baud); 858 859 port->read_status_mask = USART_SR_ORE; 860 if (termios->c_iflag & INPCK) 861 port->read_status_mask |= USART_SR_PE | USART_SR_FE; 862 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 863 port->read_status_mask |= USART_SR_FE; 864 865 /* Characters to ignore */ 866 port->ignore_status_mask = 0; 867 if (termios->c_iflag & IGNPAR) 868 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; 869 if (termios->c_iflag & IGNBRK) { 870 port->ignore_status_mask |= USART_SR_FE; 871 /* 872 * If we're ignoring parity and break indicators, 873 * ignore overruns too (for real raw support). 874 */ 875 if (termios->c_iflag & IGNPAR) 876 port->ignore_status_mask |= USART_SR_ORE; 877 } 878 879 /* Ignore all characters if CREAD is not set */ 880 if ((termios->c_cflag & CREAD) == 0) 881 port->ignore_status_mask |= USART_SR_DUMMY_RX; 882 883 if (stm32_port->rx_ch) 884 cr3 |= USART_CR3_DMAR; 885 886 if (rs485conf->flags & SER_RS485_ENABLED) { 887 stm32_usart_config_reg_rs485(&cr1, &cr3, 888 rs485conf->delay_rts_before_send, 889 rs485conf->delay_rts_after_send, 890 baud); 891 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { 892 cr3 &= ~USART_CR3_DEP; 893 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 894 } else { 895 cr3 |= USART_CR3_DEP; 896 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 897 } 898 899 } else { 900 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP); 901 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); 902 } 903 904 writel_relaxed(cr3, port->membase + ofs->cr3); 905 writel_relaxed(cr2, port->membase + ofs->cr2); 906 writel_relaxed(cr1, port->membase + ofs->cr1); 907 908 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 909 spin_unlock_irqrestore(&port->lock, flags); 910 } 911 912 static const char *stm32_usart_type(struct uart_port *port) 913 { 914 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; 915 } 916 917 static void stm32_usart_release_port(struct uart_port *port) 918 { 919 } 920 921 static int stm32_usart_request_port(struct uart_port *port) 922 { 923 return 0; 924 } 925 926 static void stm32_usart_config_port(struct uart_port *port, int flags) 927 { 928 if (flags & UART_CONFIG_TYPE) 929 port->type = PORT_STM32; 930 } 931 932 static int 933 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser) 934 { 935 /* No user changeable parameters */ 936 return -EINVAL; 937 } 938 939 static void stm32_usart_pm(struct uart_port *port, unsigned int state, 940 unsigned int oldstate) 941 { 942 struct stm32_port *stm32port = container_of(port, 943 struct stm32_port, port); 944 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 945 const struct stm32_usart_config *cfg = &stm32port->info->cfg; 946 unsigned long flags = 0; 947 948 switch (state) { 949 case UART_PM_STATE_ON: 950 pm_runtime_get_sync(port->dev); 951 break; 952 case UART_PM_STATE_OFF: 953 spin_lock_irqsave(&port->lock, flags); 954 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 955 spin_unlock_irqrestore(&port->lock, flags); 956 pm_runtime_put_sync(port->dev); 957 break; 958 } 959 } 960 961 static const struct uart_ops stm32_uart_ops = { 962 .tx_empty = stm32_usart_tx_empty, 963 .set_mctrl = stm32_usart_set_mctrl, 964 .get_mctrl = stm32_usart_get_mctrl, 965 .stop_tx = stm32_usart_stop_tx, 966 .start_tx = stm32_usart_start_tx, 967 .throttle = stm32_usart_throttle, 968 .unthrottle = stm32_usart_unthrottle, 969 .stop_rx = stm32_usart_stop_rx, 970 .enable_ms = stm32_usart_enable_ms, 971 .break_ctl = stm32_usart_break_ctl, 972 .startup = stm32_usart_startup, 973 .shutdown = stm32_usart_shutdown, 974 .set_termios = stm32_usart_set_termios, 975 .pm = stm32_usart_pm, 976 .type = stm32_usart_type, 977 .release_port = stm32_usart_release_port, 978 .request_port = stm32_usart_request_port, 979 .config_port = stm32_usart_config_port, 980 .verify_port = stm32_usart_verify_port, 981 }; 982 983 static void stm32_usart_deinit_port(struct stm32_port *stm32port) 984 { 985 clk_disable_unprepare(stm32port->clk); 986 } 987 988 static int stm32_usart_init_port(struct stm32_port *stm32port, 989 struct platform_device *pdev) 990 { 991 struct uart_port *port = &stm32port->port; 992 struct resource *res; 993 int ret, irq; 994 995 irq = platform_get_irq(pdev, 0); 996 if (irq <= 0) 997 return irq ? : -ENODEV; 998 999 port->iotype = UPIO_MEM; 1000 port->flags = UPF_BOOT_AUTOCONF; 1001 port->ops = &stm32_uart_ops; 1002 port->dev = &pdev->dev; 1003 port->fifosize = stm32port->info->cfg.fifosize; 1004 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); 1005 port->irq = irq; 1006 port->rs485_config = stm32_usart_config_rs485; 1007 1008 ret = stm32_usart_init_rs485(port, pdev); 1009 if (ret) 1010 return ret; 1011 1012 if (stm32port->info->cfg.has_wakeup) { 1013 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); 1014 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) 1015 return stm32port->wakeirq ? : -ENODEV; 1016 } 1017 1018 stm32port->fifoen = stm32port->info->cfg.has_fifo; 1019 1020 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1021 port->membase = devm_ioremap_resource(&pdev->dev, res); 1022 if (IS_ERR(port->membase)) 1023 return PTR_ERR(port->membase); 1024 port->mapbase = res->start; 1025 1026 spin_lock_init(&port->lock); 1027 1028 stm32port->clk = devm_clk_get(&pdev->dev, NULL); 1029 if (IS_ERR(stm32port->clk)) 1030 return PTR_ERR(stm32port->clk); 1031 1032 /* Ensure that clk rate is correct by enabling the clk */ 1033 ret = clk_prepare_enable(stm32port->clk); 1034 if (ret) 1035 return ret; 1036 1037 stm32port->port.uartclk = clk_get_rate(stm32port->clk); 1038 if (!stm32port->port.uartclk) { 1039 ret = -EINVAL; 1040 goto err_clk; 1041 } 1042 1043 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); 1044 if (IS_ERR(stm32port->gpios)) { 1045 ret = PTR_ERR(stm32port->gpios); 1046 goto err_clk; 1047 } 1048 1049 /* 1050 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" 1051 * properties should not be specified. 1052 */ 1053 if (stm32port->hw_flow_control) { 1054 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || 1055 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { 1056 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); 1057 ret = -EINVAL; 1058 goto err_clk; 1059 } 1060 } 1061 1062 return ret; 1063 1064 err_clk: 1065 clk_disable_unprepare(stm32port->clk); 1066 1067 return ret; 1068 } 1069 1070 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev) 1071 { 1072 struct device_node *np = pdev->dev.of_node; 1073 int id; 1074 1075 if (!np) 1076 return NULL; 1077 1078 id = of_alias_get_id(np, "serial"); 1079 if (id < 0) { 1080 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); 1081 return NULL; 1082 } 1083 1084 if (WARN_ON(id >= STM32_MAX_PORTS)) 1085 return NULL; 1086 1087 stm32_ports[id].hw_flow_control = 1088 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || 1089 of_property_read_bool (np, "uart-has-rtscts"); 1090 stm32_ports[id].port.line = id; 1091 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; 1092 stm32_ports[id].cr3_irq = 0; 1093 stm32_ports[id].last_res = RX_BUF_L; 1094 return &stm32_ports[id]; 1095 } 1096 1097 #ifdef CONFIG_OF 1098 static const struct of_device_id stm32_match[] = { 1099 { .compatible = "st,stm32-uart", .data = &stm32f4_info}, 1100 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info}, 1101 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info}, 1102 {}, 1103 }; 1104 1105 MODULE_DEVICE_TABLE(of, stm32_match); 1106 #endif 1107 1108 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port, 1109 struct platform_device *pdev) 1110 { 1111 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1112 struct uart_port *port = &stm32port->port; 1113 struct device *dev = &pdev->dev; 1114 struct dma_slave_config config; 1115 struct dma_async_tx_descriptor *desc = NULL; 1116 int ret; 1117 1118 /* Request DMA RX channel */ 1119 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); 1120 if (!stm32port->rx_ch) { 1121 dev_info(dev, "rx dma alloc failed\n"); 1122 return -ENODEV; 1123 } 1124 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, 1125 &stm32port->rx_dma_buf, 1126 GFP_KERNEL); 1127 if (!stm32port->rx_buf) { 1128 ret = -ENOMEM; 1129 goto alloc_err; 1130 } 1131 1132 /* Configure DMA channel */ 1133 memset(&config, 0, sizeof(config)); 1134 config.src_addr = port->mapbase + ofs->rdr; 1135 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1136 1137 ret = dmaengine_slave_config(stm32port->rx_ch, &config); 1138 if (ret < 0) { 1139 dev_err(dev, "rx dma channel config failed\n"); 1140 ret = -ENODEV; 1141 goto config_err; 1142 } 1143 1144 /* Prepare a DMA cyclic transaction */ 1145 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, 1146 stm32port->rx_dma_buf, 1147 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM, 1148 DMA_PREP_INTERRUPT); 1149 if (!desc) { 1150 dev_err(dev, "rx dma prep cyclic failed\n"); 1151 ret = -ENODEV; 1152 goto config_err; 1153 } 1154 1155 /* No callback as dma buffer is drained on usart interrupt */ 1156 desc->callback = NULL; 1157 desc->callback_param = NULL; 1158 1159 /* Push current DMA transaction in the pending queue */ 1160 ret = dma_submit_error(dmaengine_submit(desc)); 1161 if (ret) { 1162 dmaengine_terminate_sync(stm32port->rx_ch); 1163 goto config_err; 1164 } 1165 1166 /* Issue pending DMA requests */ 1167 dma_async_issue_pending(stm32port->rx_ch); 1168 1169 return 0; 1170 1171 config_err: 1172 dma_free_coherent(&pdev->dev, 1173 RX_BUF_L, stm32port->rx_buf, 1174 stm32port->rx_dma_buf); 1175 1176 alloc_err: 1177 dma_release_channel(stm32port->rx_ch); 1178 stm32port->rx_ch = NULL; 1179 1180 return ret; 1181 } 1182 1183 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port, 1184 struct platform_device *pdev) 1185 { 1186 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; 1187 struct uart_port *port = &stm32port->port; 1188 struct device *dev = &pdev->dev; 1189 struct dma_slave_config config; 1190 int ret; 1191 1192 stm32port->tx_dma_busy = false; 1193 1194 /* Request DMA TX channel */ 1195 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); 1196 if (!stm32port->tx_ch) { 1197 dev_info(dev, "tx dma alloc failed\n"); 1198 return -ENODEV; 1199 } 1200 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, 1201 &stm32port->tx_dma_buf, 1202 GFP_KERNEL); 1203 if (!stm32port->tx_buf) { 1204 ret = -ENOMEM; 1205 goto alloc_err; 1206 } 1207 1208 /* Configure DMA channel */ 1209 memset(&config, 0, sizeof(config)); 1210 config.dst_addr = port->mapbase + ofs->tdr; 1211 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1212 1213 ret = dmaengine_slave_config(stm32port->tx_ch, &config); 1214 if (ret < 0) { 1215 dev_err(dev, "tx dma channel config failed\n"); 1216 ret = -ENODEV; 1217 goto config_err; 1218 } 1219 1220 return 0; 1221 1222 config_err: 1223 dma_free_coherent(&pdev->dev, 1224 TX_BUF_L, stm32port->tx_buf, 1225 stm32port->tx_dma_buf); 1226 1227 alloc_err: 1228 dma_release_channel(stm32port->tx_ch); 1229 stm32port->tx_ch = NULL; 1230 1231 return ret; 1232 } 1233 1234 static int stm32_usart_serial_probe(struct platform_device *pdev) 1235 { 1236 struct stm32_port *stm32port; 1237 int ret; 1238 1239 stm32port = stm32_usart_of_get_port(pdev); 1240 if (!stm32port) 1241 return -ENODEV; 1242 1243 stm32port->info = of_device_get_match_data(&pdev->dev); 1244 if (!stm32port->info) 1245 return -EINVAL; 1246 1247 ret = stm32_usart_init_port(stm32port, pdev); 1248 if (ret) 1249 return ret; 1250 1251 if (stm32port->wakeirq > 0) { 1252 ret = device_init_wakeup(&pdev->dev, true); 1253 if (ret) 1254 goto err_uninit; 1255 1256 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, 1257 stm32port->wakeirq); 1258 if (ret) 1259 goto err_nowup; 1260 1261 device_set_wakeup_enable(&pdev->dev, false); 1262 } 1263 1264 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev); 1265 if (ret) 1266 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); 1267 1268 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev); 1269 if (ret) 1270 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); 1271 1272 platform_set_drvdata(pdev, &stm32port->port); 1273 1274 pm_runtime_get_noresume(&pdev->dev); 1275 pm_runtime_set_active(&pdev->dev); 1276 pm_runtime_enable(&pdev->dev); 1277 1278 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); 1279 if (ret) 1280 goto err_port; 1281 1282 pm_runtime_put_sync(&pdev->dev); 1283 1284 return 0; 1285 1286 err_port: 1287 pm_runtime_disable(&pdev->dev); 1288 pm_runtime_set_suspended(&pdev->dev); 1289 pm_runtime_put_noidle(&pdev->dev); 1290 1291 if (stm32port->rx_ch) { 1292 dmaengine_terminate_async(stm32port->rx_ch); 1293 dma_release_channel(stm32port->rx_ch); 1294 } 1295 1296 if (stm32port->rx_dma_buf) 1297 dma_free_coherent(&pdev->dev, 1298 RX_BUF_L, stm32port->rx_buf, 1299 stm32port->rx_dma_buf); 1300 1301 if (stm32port->tx_ch) { 1302 dmaengine_terminate_async(stm32port->tx_ch); 1303 dma_release_channel(stm32port->tx_ch); 1304 } 1305 1306 if (stm32port->tx_dma_buf) 1307 dma_free_coherent(&pdev->dev, 1308 TX_BUF_L, stm32port->tx_buf, 1309 stm32port->tx_dma_buf); 1310 1311 if (stm32port->wakeirq > 0) 1312 dev_pm_clear_wake_irq(&pdev->dev); 1313 1314 err_nowup: 1315 if (stm32port->wakeirq > 0) 1316 device_init_wakeup(&pdev->dev, false); 1317 1318 err_uninit: 1319 stm32_usart_deinit_port(stm32port); 1320 1321 return ret; 1322 } 1323 1324 static int stm32_usart_serial_remove(struct platform_device *pdev) 1325 { 1326 struct uart_port *port = platform_get_drvdata(pdev); 1327 struct stm32_port *stm32_port = to_stm32_port(port); 1328 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1329 int err; 1330 1331 pm_runtime_get_sync(&pdev->dev); 1332 err = uart_remove_one_port(&stm32_usart_driver, port); 1333 if (err) 1334 return(err); 1335 1336 pm_runtime_disable(&pdev->dev); 1337 pm_runtime_set_suspended(&pdev->dev); 1338 pm_runtime_put_noidle(&pdev->dev); 1339 1340 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); 1341 1342 if (stm32_port->rx_ch) { 1343 dmaengine_terminate_async(stm32_port->rx_ch); 1344 dma_release_channel(stm32_port->rx_ch); 1345 } 1346 1347 if (stm32_port->rx_dma_buf) 1348 dma_free_coherent(&pdev->dev, 1349 RX_BUF_L, stm32_port->rx_buf, 1350 stm32_port->rx_dma_buf); 1351 1352 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); 1353 1354 if (stm32_port->tx_ch) { 1355 dmaengine_terminate_async(stm32_port->tx_ch); 1356 dma_release_channel(stm32_port->tx_ch); 1357 } 1358 1359 if (stm32_port->tx_dma_buf) 1360 dma_free_coherent(&pdev->dev, 1361 TX_BUF_L, stm32_port->tx_buf, 1362 stm32_port->tx_dma_buf); 1363 1364 if (stm32_port->wakeirq > 0) { 1365 dev_pm_clear_wake_irq(&pdev->dev); 1366 device_init_wakeup(&pdev->dev, false); 1367 } 1368 1369 stm32_usart_deinit_port(stm32_port); 1370 1371 return 0; 1372 } 1373 1374 #ifdef CONFIG_SERIAL_STM32_CONSOLE 1375 static void stm32_usart_console_putchar(struct uart_port *port, int ch) 1376 { 1377 struct stm32_port *stm32_port = to_stm32_port(port); 1378 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1379 1380 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) 1381 cpu_relax(); 1382 1383 writel_relaxed(ch, port->membase + ofs->tdr); 1384 } 1385 1386 static void stm32_usart_console_write(struct console *co, const char *s, 1387 unsigned int cnt) 1388 { 1389 struct uart_port *port = &stm32_ports[co->index].port; 1390 struct stm32_port *stm32_port = to_stm32_port(port); 1391 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1392 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1393 unsigned long flags; 1394 u32 old_cr1, new_cr1; 1395 int locked = 1; 1396 1397 local_irq_save(flags); 1398 if (port->sysrq) 1399 locked = 0; 1400 else if (oops_in_progress) 1401 locked = spin_trylock(&port->lock); 1402 else 1403 spin_lock(&port->lock); 1404 1405 /* Save and disable interrupts, enable the transmitter */ 1406 old_cr1 = readl_relaxed(port->membase + ofs->cr1); 1407 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK; 1408 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); 1409 writel_relaxed(new_cr1, port->membase + ofs->cr1); 1410 1411 uart_console_write(port, s, cnt, stm32_usart_console_putchar); 1412 1413 /* Restore interrupt state */ 1414 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1415 1416 if (locked) 1417 spin_unlock(&port->lock); 1418 local_irq_restore(flags); 1419 } 1420 1421 static int stm32_usart_console_setup(struct console *co, char *options) 1422 { 1423 struct stm32_port *stm32port; 1424 int baud = 9600; 1425 int bits = 8; 1426 int parity = 'n'; 1427 int flow = 'n'; 1428 1429 if (co->index >= STM32_MAX_PORTS) 1430 return -ENODEV; 1431 1432 stm32port = &stm32_ports[co->index]; 1433 1434 /* 1435 * This driver does not support early console initialization 1436 * (use ARM early printk support instead), so we only expect 1437 * this to be called during the uart port registration when the 1438 * driver gets probed and the port should be mapped at that point. 1439 */ 1440 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) 1441 return -ENXIO; 1442 1443 if (options) 1444 uart_parse_options(options, &baud, &parity, &bits, &flow); 1445 1446 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); 1447 } 1448 1449 static struct console stm32_console = { 1450 .name = STM32_SERIAL_NAME, 1451 .device = uart_console_device, 1452 .write = stm32_usart_console_write, 1453 .setup = stm32_usart_console_setup, 1454 .flags = CON_PRINTBUFFER, 1455 .index = -1, 1456 .data = &stm32_usart_driver, 1457 }; 1458 1459 #define STM32_SERIAL_CONSOLE (&stm32_console) 1460 1461 #else 1462 #define STM32_SERIAL_CONSOLE NULL 1463 #endif /* CONFIG_SERIAL_STM32_CONSOLE */ 1464 1465 static struct uart_driver stm32_usart_driver = { 1466 .driver_name = DRIVER_NAME, 1467 .dev_name = STM32_SERIAL_NAME, 1468 .major = 0, 1469 .minor = 0, 1470 .nr = STM32_MAX_PORTS, 1471 .cons = STM32_SERIAL_CONSOLE, 1472 }; 1473 1474 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port, 1475 bool enable) 1476 { 1477 struct stm32_port *stm32_port = to_stm32_port(port); 1478 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1479 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; 1480 u32 val; 1481 1482 if (stm32_port->wakeirq <= 0) 1483 return; 1484 1485 if (enable) { 1486 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1487 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); 1488 val = readl_relaxed(port->membase + ofs->cr3); 1489 val &= ~USART_CR3_WUS_MASK; 1490 /* Enable Wake up interrupt from low power on start bit */ 1491 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE; 1492 writel_relaxed(val, port->membase + ofs->cr3); 1493 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1494 } else { 1495 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); 1496 } 1497 } 1498 1499 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev) 1500 { 1501 struct uart_port *port = dev_get_drvdata(dev); 1502 1503 uart_suspend_port(&stm32_usart_driver, port); 1504 1505 if (device_may_wakeup(dev)) 1506 stm32_usart_serial_en_wakeup(port, true); 1507 else 1508 stm32_usart_serial_en_wakeup(port, false); 1509 1510 /* 1511 * When "no_console_suspend" is enabled, keep the pinctrl default state 1512 * and rely on bootloader stage to restore this state upon resume. 1513 * Otherwise, apply the idle or sleep states depending on wakeup 1514 * capabilities. 1515 */ 1516 if (console_suspend_enabled || !uart_console(port)) { 1517 if (device_may_wakeup(dev)) 1518 pinctrl_pm_select_idle_state(dev); 1519 else 1520 pinctrl_pm_select_sleep_state(dev); 1521 } 1522 1523 return 0; 1524 } 1525 1526 static int __maybe_unused stm32_usart_serial_resume(struct device *dev) 1527 { 1528 struct uart_port *port = dev_get_drvdata(dev); 1529 1530 pinctrl_pm_select_default_state(dev); 1531 1532 if (device_may_wakeup(dev)) 1533 stm32_usart_serial_en_wakeup(port, false); 1534 1535 return uart_resume_port(&stm32_usart_driver, port); 1536 } 1537 1538 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev) 1539 { 1540 struct uart_port *port = dev_get_drvdata(dev); 1541 struct stm32_port *stm32port = container_of(port, 1542 struct stm32_port, port); 1543 1544 clk_disable_unprepare(stm32port->clk); 1545 1546 return 0; 1547 } 1548 1549 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev) 1550 { 1551 struct uart_port *port = dev_get_drvdata(dev); 1552 struct stm32_port *stm32port = container_of(port, 1553 struct stm32_port, port); 1554 1555 return clk_prepare_enable(stm32port->clk); 1556 } 1557 1558 static const struct dev_pm_ops stm32_serial_pm_ops = { 1559 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend, 1560 stm32_usart_runtime_resume, NULL) 1561 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend, 1562 stm32_usart_serial_resume) 1563 }; 1564 1565 static struct platform_driver stm32_serial_driver = { 1566 .probe = stm32_usart_serial_probe, 1567 .remove = stm32_usart_serial_remove, 1568 .driver = { 1569 .name = DRIVER_NAME, 1570 .pm = &stm32_serial_pm_ops, 1571 .of_match_table = of_match_ptr(stm32_match), 1572 }, 1573 }; 1574 1575 static int __init stm32_usart_init(void) 1576 { 1577 static char banner[] __initdata = "STM32 USART driver initialized"; 1578 int ret; 1579 1580 pr_info("%s\n", banner); 1581 1582 ret = uart_register_driver(&stm32_usart_driver); 1583 if (ret) 1584 return ret; 1585 1586 ret = platform_driver_register(&stm32_serial_driver); 1587 if (ret) 1588 uart_unregister_driver(&stm32_usart_driver); 1589 1590 return ret; 1591 } 1592 1593 static void __exit stm32_usart_exit(void) 1594 { 1595 platform_driver_unregister(&stm32_serial_driver); 1596 uart_unregister_driver(&stm32_usart_driver); 1597 } 1598 1599 module_init(stm32_usart_init); 1600 module_exit(stm32_usart_exit); 1601 1602 MODULE_ALIAS("platform:" DRIVER_NAME); 1603 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver"); 1604 MODULE_LICENSE("GPL v2"); 1605