spi-sun6i.c (9a3ef9df22ec1fe8d49b219c181c039f25c3296d) | spi-sun6i.c (5197da036398863c90db90b2ea53760fdaec5d86) |
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1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2012 - 2014 Allwinner Tech 4 * Pan Nan <pannan@allwinnertech.com> 5 * 6 * Copyright (C) 2014 Maxime Ripard 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ --- 45 unchanged lines hidden (view full) --- 54#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff 55#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 56#define SUN6I_FIFO_CTL_RF_RST BIT(15) 57#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff 58#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 59#define SUN6I_FIFO_CTL_TF_RST BIT(31) 60 61#define SUN6I_FIFO_STA_REG 0x1c | 1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2012 - 2014 Allwinner Tech 4 * Pan Nan <pannan@allwinnertech.com> 5 * 6 * Copyright (C) 2014 Maxime Ripard 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ --- 45 unchanged lines hidden (view full) --- 54#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff 55#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 56#define SUN6I_FIFO_CTL_RF_RST BIT(15) 57#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff 58#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 59#define SUN6I_FIFO_CTL_TF_RST BIT(31) 60 61#define SUN6I_FIFO_STA_REG 0x1c |
62#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f 63#define SUN6I_FIFO_STA_RF_CNT_BITS 0 | 62#define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0) |
64#define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16) 65 66#define SUN6I_CLK_CTL_REG 0x24 67#define SUN6I_CLK_CTL_CDR2_MASK 0xff 68#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) 69#define SUN6I_CLK_CTL_CDR1_MASK 0xf 70#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) 71#define SUN6I_CLK_CTL_DRS BIT(12) --- 29 unchanged lines hidden (view full) --- 101 return readl(sspi->base_addr + reg); 102} 103 104static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) 105{ 106 writel(value, sspi->base_addr + reg); 107} 108 | 63#define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16) 64 65#define SUN6I_CLK_CTL_REG 0x24 66#define SUN6I_CLK_CTL_CDR2_MASK 0xff 67#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) 68#define SUN6I_CLK_CTL_CDR1_MASK 0xf 69#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) 70#define SUN6I_CLK_CTL_DRS BIT(12) --- 29 unchanged lines hidden (view full) --- 100 return readl(sspi->base_addr + reg); 101} 102 103static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) 104{ 105 writel(value, sspi->base_addr + reg); 106} 107 |
108static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi) 109{ 110 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 111 112 return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg); 113} 114 |
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109static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) 110{ 111 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 112 113 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg); 114} 115 116static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) --- 9 unchanged lines hidden (view full) --- 126 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 127 128 reg &= ~mask; 129 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 130} 131 132static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) 133{ | 115static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) 116{ 117 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 118 119 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg); 120} 121 122static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) --- 9 unchanged lines hidden (view full) --- 132 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 133 134 reg &= ~mask; 135 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 136} 137 138static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) 139{ |
134 u32 reg, cnt; | 140 u32 cnt; |
135 u8 byte; 136 137 /* See how much data is available */ | 141 u8 byte; 142 143 /* See how much data is available */ |
138 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 139 reg &= SUN6I_FIFO_STA_RF_CNT_MASK; 140 cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS; | 144 cnt = sun6i_spi_get_rx_fifo_count(sspi); |
141 142 if (len > cnt) 143 len = cnt; 144 145 while (len--) { 146 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); 147 if (sspi->rx_buf) 148 *sspi->rx_buf++ = byte; --- 413 unchanged lines hidden --- | 145 146 if (len > cnt) 147 len = cnt; 148 149 while (len--) { 150 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); 151 if (sspi->rx_buf) 152 *sspi->rx_buf++ = byte; --- 413 unchanged lines hidden --- |