1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2012 - 2014 Allwinner Tech 4 * Pan Nan <pannan@allwinnertech.com> 5 * 6 * Copyright (C) 2014 Maxime Ripard 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 22 #include <linux/spi/spi.h> 23 24 #define SUN6I_FIFO_DEPTH 128 25 #define SUN8I_FIFO_DEPTH 64 26 27 #define SUN6I_GBL_CTL_REG 0x04 28 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) 29 #define SUN6I_GBL_CTL_MASTER BIT(1) 30 #define SUN6I_GBL_CTL_TP BIT(7) 31 #define SUN6I_GBL_CTL_RST BIT(31) 32 33 #define SUN6I_TFR_CTL_REG 0x08 34 #define SUN6I_TFR_CTL_CPHA BIT(0) 35 #define SUN6I_TFR_CTL_CPOL BIT(1) 36 #define SUN6I_TFR_CTL_SPOL BIT(2) 37 #define SUN6I_TFR_CTL_CS_MASK 0x30 38 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) 39 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) 40 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) 41 #define SUN6I_TFR_CTL_DHB BIT(8) 42 #define SUN6I_TFR_CTL_FBS BIT(12) 43 #define SUN6I_TFR_CTL_XCH BIT(31) 44 45 #define SUN6I_INT_CTL_REG 0x10 46 #define SUN6I_INT_CTL_RF_RDY BIT(0) 47 #define SUN6I_INT_CTL_TF_ERQ BIT(4) 48 #define SUN6I_INT_CTL_RF_OVF BIT(8) 49 #define SUN6I_INT_CTL_TC BIT(12) 50 51 #define SUN6I_INT_STA_REG 0x14 52 53 #define SUN6I_FIFO_CTL_REG 0x18 54 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff 55 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 56 #define SUN6I_FIFO_CTL_RF_RST BIT(15) 57 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff 58 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 59 #define SUN6I_FIFO_CTL_TF_RST BIT(31) 60 61 #define SUN6I_FIFO_STA_REG 0x1c 62 #define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f 63 #define SUN6I_FIFO_STA_RF_CNT_BITS 0 64 #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16) 65 66 #define SUN6I_CLK_CTL_REG 0x24 67 #define SUN6I_CLK_CTL_CDR2_MASK 0xff 68 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) 69 #define SUN6I_CLK_CTL_CDR1_MASK 0xf 70 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) 71 #define SUN6I_CLK_CTL_DRS BIT(12) 72 73 #define SUN6I_MAX_XFER_SIZE 0xffffff 74 75 #define SUN6I_BURST_CNT_REG 0x30 76 77 #define SUN6I_XMIT_CNT_REG 0x34 78 79 #define SUN6I_BURST_CTL_CNT_REG 0x38 80 81 #define SUN6I_TXDATA_REG 0x200 82 #define SUN6I_RXDATA_REG 0x300 83 84 struct sun6i_spi { 85 struct spi_master *master; 86 void __iomem *base_addr; 87 struct clk *hclk; 88 struct clk *mclk; 89 struct reset_control *rstc; 90 91 struct completion done; 92 93 const u8 *tx_buf; 94 u8 *rx_buf; 95 int len; 96 unsigned long fifo_depth; 97 }; 98 99 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) 100 { 101 return readl(sspi->base_addr + reg); 102 } 103 104 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) 105 { 106 writel(value, sspi->base_addr + reg); 107 } 108 109 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) 110 { 111 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 112 113 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg); 114 } 115 116 static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) 117 { 118 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 119 120 reg |= mask; 121 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 122 } 123 124 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) 125 { 126 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 127 128 reg &= ~mask; 129 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 130 } 131 132 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) 133 { 134 u32 reg, cnt; 135 u8 byte; 136 137 /* See how much data is available */ 138 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 139 reg &= SUN6I_FIFO_STA_RF_CNT_MASK; 140 cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS; 141 142 if (len > cnt) 143 len = cnt; 144 145 while (len--) { 146 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); 147 if (sspi->rx_buf) 148 *sspi->rx_buf++ = byte; 149 } 150 } 151 152 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) 153 { 154 u32 cnt; 155 u8 byte; 156 157 /* See how much data we can fit */ 158 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); 159 160 len = min3(len, (int)cnt, sspi->len); 161 162 while (len--) { 163 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; 164 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); 165 sspi->len--; 166 } 167 } 168 169 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) 170 { 171 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); 172 u32 reg; 173 174 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 175 reg &= ~SUN6I_TFR_CTL_CS_MASK; 176 reg |= SUN6I_TFR_CTL_CS(spi->chip_select); 177 178 if (enable) 179 reg |= SUN6I_TFR_CTL_CS_LEVEL; 180 else 181 reg &= ~SUN6I_TFR_CTL_CS_LEVEL; 182 183 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 184 } 185 186 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) 187 { 188 return SUN6I_MAX_XFER_SIZE - 1; 189 } 190 191 static int sun6i_spi_transfer_one(struct spi_master *master, 192 struct spi_device *spi, 193 struct spi_transfer *tfr) 194 { 195 struct sun6i_spi *sspi = spi_master_get_devdata(master); 196 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout; 197 unsigned int start, end, tx_time; 198 unsigned int trig_level; 199 unsigned int tx_len = 0; 200 int ret = 0; 201 u32 reg; 202 203 if (tfr->len > SUN6I_MAX_XFER_SIZE) 204 return -EINVAL; 205 206 reinit_completion(&sspi->done); 207 sspi->tx_buf = tfr->tx_buf; 208 sspi->rx_buf = tfr->rx_buf; 209 sspi->len = tfr->len; 210 211 /* Clear pending interrupts */ 212 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); 213 214 /* Reset FIFO */ 215 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 216 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); 217 218 /* 219 * Setup FIFO interrupt trigger level 220 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded 221 * value used in old generation of Allwinner SPI controller. 222 * (See spi-sun4i.c) 223 */ 224 trig_level = sspi->fifo_depth / 4 * 3; 225 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 226 (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | 227 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS)); 228 229 /* 230 * Setup the transfer control register: Chip Select, 231 * polarities, etc. 232 */ 233 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 234 235 if (spi->mode & SPI_CPOL) 236 reg |= SUN6I_TFR_CTL_CPOL; 237 else 238 reg &= ~SUN6I_TFR_CTL_CPOL; 239 240 if (spi->mode & SPI_CPHA) 241 reg |= SUN6I_TFR_CTL_CPHA; 242 else 243 reg &= ~SUN6I_TFR_CTL_CPHA; 244 245 if (spi->mode & SPI_LSB_FIRST) 246 reg |= SUN6I_TFR_CTL_FBS; 247 else 248 reg &= ~SUN6I_TFR_CTL_FBS; 249 250 /* 251 * If it's a TX only transfer, we don't want to fill the RX 252 * FIFO with bogus data 253 */ 254 if (sspi->rx_buf) 255 reg &= ~SUN6I_TFR_CTL_DHB; 256 else 257 reg |= SUN6I_TFR_CTL_DHB; 258 259 /* We want to control the chip select manually */ 260 reg |= SUN6I_TFR_CTL_CS_MANUAL; 261 262 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 263 264 /* Ensure that we have a parent clock fast enough */ 265 mclk_rate = clk_get_rate(sspi->mclk); 266 if (mclk_rate < (2 * tfr->speed_hz)) { 267 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); 268 mclk_rate = clk_get_rate(sspi->mclk); 269 } 270 271 /* 272 * Setup clock divider. 273 * 274 * We have two choices there. Either we can use the clock 275 * divide rate 1, which is calculated thanks to this formula: 276 * SPI_CLK = MOD_CLK / (2 ^ cdr) 277 * Or we can use CDR2, which is calculated with the formula: 278 * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) 279 * Wether we use the former or the latter is set through the 280 * DRS bit. 281 * 282 * First try CDR2, and if we can't reach the expected 283 * frequency, fall back to CDR1. 284 */ 285 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); 286 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); 287 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { 288 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; 289 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); 290 } else { 291 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); 292 reg = SUN6I_CLK_CTL_CDR1(div); 293 tfr->effective_speed_hz = mclk_rate / (1 << div); 294 } 295 296 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); 297 298 /* Setup the transfer now... */ 299 if (sspi->tx_buf) 300 tx_len = tfr->len; 301 302 /* Setup the counters */ 303 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); 304 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len); 305 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len); 306 307 /* Fill the TX FIFO */ 308 sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); 309 310 /* Enable the interrupts */ 311 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); 312 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC | 313 SUN6I_INT_CTL_RF_RDY); 314 if (tx_len > sspi->fifo_depth) 315 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); 316 317 /* Start the transfer */ 318 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 319 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); 320 321 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); 322 start = jiffies; 323 timeout = wait_for_completion_timeout(&sspi->done, 324 msecs_to_jiffies(tx_time)); 325 end = jiffies; 326 if (!timeout) { 327 dev_warn(&master->dev, 328 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", 329 dev_name(&spi->dev), tfr->len, tfr->speed_hz, 330 jiffies_to_msecs(end - start), tx_time); 331 ret = -ETIMEDOUT; 332 } 333 334 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); 335 336 return ret; 337 } 338 339 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) 340 { 341 struct sun6i_spi *sspi = dev_id; 342 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); 343 344 /* Transfer complete */ 345 if (status & SUN6I_INT_CTL_TC) { 346 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); 347 sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); 348 complete(&sspi->done); 349 return IRQ_HANDLED; 350 } 351 352 /* Receive FIFO 3/4 full */ 353 if (status & SUN6I_INT_CTL_RF_RDY) { 354 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); 355 /* Only clear the interrupt _after_ draining the FIFO */ 356 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY); 357 return IRQ_HANDLED; 358 } 359 360 /* Transmit FIFO 3/4 empty */ 361 if (status & SUN6I_INT_CTL_TF_ERQ) { 362 sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); 363 364 if (!sspi->len) 365 /* nothing left to transmit */ 366 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); 367 368 /* Only clear the interrupt _after_ re-seeding the FIFO */ 369 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ); 370 371 return IRQ_HANDLED; 372 } 373 374 return IRQ_NONE; 375 } 376 377 static int sun6i_spi_runtime_resume(struct device *dev) 378 { 379 struct spi_master *master = dev_get_drvdata(dev); 380 struct sun6i_spi *sspi = spi_master_get_devdata(master); 381 int ret; 382 383 ret = clk_prepare_enable(sspi->hclk); 384 if (ret) { 385 dev_err(dev, "Couldn't enable AHB clock\n"); 386 goto out; 387 } 388 389 ret = clk_prepare_enable(sspi->mclk); 390 if (ret) { 391 dev_err(dev, "Couldn't enable module clock\n"); 392 goto err; 393 } 394 395 ret = reset_control_deassert(sspi->rstc); 396 if (ret) { 397 dev_err(dev, "Couldn't deassert the device from reset\n"); 398 goto err2; 399 } 400 401 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, 402 SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); 403 404 return 0; 405 406 err2: 407 clk_disable_unprepare(sspi->mclk); 408 err: 409 clk_disable_unprepare(sspi->hclk); 410 out: 411 return ret; 412 } 413 414 static int sun6i_spi_runtime_suspend(struct device *dev) 415 { 416 struct spi_master *master = dev_get_drvdata(dev); 417 struct sun6i_spi *sspi = spi_master_get_devdata(master); 418 419 reset_control_assert(sspi->rstc); 420 clk_disable_unprepare(sspi->mclk); 421 clk_disable_unprepare(sspi->hclk); 422 423 return 0; 424 } 425 426 static int sun6i_spi_probe(struct platform_device *pdev) 427 { 428 struct spi_master *master; 429 struct sun6i_spi *sspi; 430 int ret = 0, irq; 431 432 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); 433 if (!master) { 434 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 435 return -ENOMEM; 436 } 437 438 platform_set_drvdata(pdev, master); 439 sspi = spi_master_get_devdata(master); 440 441 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0); 442 if (IS_ERR(sspi->base_addr)) { 443 ret = PTR_ERR(sspi->base_addr); 444 goto err_free_master; 445 } 446 447 irq = platform_get_irq(pdev, 0); 448 if (irq < 0) { 449 ret = -ENXIO; 450 goto err_free_master; 451 } 452 453 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, 454 0, "sun6i-spi", sspi); 455 if (ret) { 456 dev_err(&pdev->dev, "Cannot request IRQ\n"); 457 goto err_free_master; 458 } 459 460 sspi->master = master; 461 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); 462 463 master->max_speed_hz = 100 * 1000 * 1000; 464 master->min_speed_hz = 3 * 1000; 465 master->use_gpio_descriptors = true; 466 master->set_cs = sun6i_spi_set_cs; 467 master->transfer_one = sun6i_spi_transfer_one; 468 master->num_chipselect = 4; 469 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 470 master->bits_per_word_mask = SPI_BPW_MASK(8); 471 master->dev.of_node = pdev->dev.of_node; 472 master->auto_runtime_pm = true; 473 master->max_transfer_size = sun6i_spi_max_transfer_size; 474 475 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 476 if (IS_ERR(sspi->hclk)) { 477 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 478 ret = PTR_ERR(sspi->hclk); 479 goto err_free_master; 480 } 481 482 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); 483 if (IS_ERR(sspi->mclk)) { 484 dev_err(&pdev->dev, "Unable to acquire module clock\n"); 485 ret = PTR_ERR(sspi->mclk); 486 goto err_free_master; 487 } 488 489 init_completion(&sspi->done); 490 491 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 492 if (IS_ERR(sspi->rstc)) { 493 dev_err(&pdev->dev, "Couldn't get reset controller\n"); 494 ret = PTR_ERR(sspi->rstc); 495 goto err_free_master; 496 } 497 498 /* 499 * This wake-up/shutdown pattern is to be able to have the 500 * device woken up, even if runtime_pm is disabled 501 */ 502 ret = sun6i_spi_runtime_resume(&pdev->dev); 503 if (ret) { 504 dev_err(&pdev->dev, "Couldn't resume the device\n"); 505 goto err_free_master; 506 } 507 508 pm_runtime_set_active(&pdev->dev); 509 pm_runtime_enable(&pdev->dev); 510 pm_runtime_idle(&pdev->dev); 511 512 ret = devm_spi_register_master(&pdev->dev, master); 513 if (ret) { 514 dev_err(&pdev->dev, "cannot register SPI master\n"); 515 goto err_pm_disable; 516 } 517 518 return 0; 519 520 err_pm_disable: 521 pm_runtime_disable(&pdev->dev); 522 sun6i_spi_runtime_suspend(&pdev->dev); 523 err_free_master: 524 spi_master_put(master); 525 return ret; 526 } 527 528 static int sun6i_spi_remove(struct platform_device *pdev) 529 { 530 pm_runtime_force_suspend(&pdev->dev); 531 532 return 0; 533 } 534 535 static const struct of_device_id sun6i_spi_match[] = { 536 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, 537 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, 538 {} 539 }; 540 MODULE_DEVICE_TABLE(of, sun6i_spi_match); 541 542 static const struct dev_pm_ops sun6i_spi_pm_ops = { 543 .runtime_resume = sun6i_spi_runtime_resume, 544 .runtime_suspend = sun6i_spi_runtime_suspend, 545 }; 546 547 static struct platform_driver sun6i_spi_driver = { 548 .probe = sun6i_spi_probe, 549 .remove = sun6i_spi_remove, 550 .driver = { 551 .name = "sun6i-spi", 552 .of_match_table = sun6i_spi_match, 553 .pm = &sun6i_spi_pm_ops, 554 }, 555 }; 556 module_platform_driver(sun6i_spi_driver); 557 558 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); 559 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 560 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); 561 MODULE_LICENSE("GPL"); 562