1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2012 - 2014 Allwinner Tech 4 * Pan Nan <pannan@allwinnertech.com> 5 * 6 * Copyright (C) 2014 Maxime Ripard 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 22 #include <linux/spi/spi.h> 23 24 #define SUN6I_FIFO_DEPTH 128 25 #define SUN8I_FIFO_DEPTH 64 26 27 #define SUN6I_GBL_CTL_REG 0x04 28 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) 29 #define SUN6I_GBL_CTL_MASTER BIT(1) 30 #define SUN6I_GBL_CTL_TP BIT(7) 31 #define SUN6I_GBL_CTL_RST BIT(31) 32 33 #define SUN6I_TFR_CTL_REG 0x08 34 #define SUN6I_TFR_CTL_CPHA BIT(0) 35 #define SUN6I_TFR_CTL_CPOL BIT(1) 36 #define SUN6I_TFR_CTL_SPOL BIT(2) 37 #define SUN6I_TFR_CTL_CS_MASK 0x30 38 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) 39 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) 40 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) 41 #define SUN6I_TFR_CTL_DHB BIT(8) 42 #define SUN6I_TFR_CTL_FBS BIT(12) 43 #define SUN6I_TFR_CTL_XCH BIT(31) 44 45 #define SUN6I_INT_CTL_REG 0x10 46 #define SUN6I_INT_CTL_RF_RDY BIT(0) 47 #define SUN6I_INT_CTL_TF_ERQ BIT(4) 48 #define SUN6I_INT_CTL_RF_OVF BIT(8) 49 #define SUN6I_INT_CTL_TC BIT(12) 50 51 #define SUN6I_INT_STA_REG 0x14 52 53 #define SUN6I_FIFO_CTL_REG 0x18 54 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff 55 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 56 #define SUN6I_FIFO_CTL_RF_RST BIT(15) 57 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff 58 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 59 #define SUN6I_FIFO_CTL_TF_RST BIT(31) 60 61 #define SUN6I_FIFO_STA_REG 0x1c 62 #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0) 63 #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16) 64 65 #define SUN6I_CLK_CTL_REG 0x24 66 #define SUN6I_CLK_CTL_CDR2_MASK 0xff 67 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) 68 #define SUN6I_CLK_CTL_CDR1_MASK 0xf 69 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) 70 #define SUN6I_CLK_CTL_DRS BIT(12) 71 72 #define SUN6I_MAX_XFER_SIZE 0xffffff 73 74 #define SUN6I_BURST_CNT_REG 0x30 75 76 #define SUN6I_XMIT_CNT_REG 0x34 77 78 #define SUN6I_BURST_CTL_CNT_REG 0x38 79 80 #define SUN6I_TXDATA_REG 0x200 81 #define SUN6I_RXDATA_REG 0x300 82 83 struct sun6i_spi { 84 struct spi_master *master; 85 void __iomem *base_addr; 86 struct clk *hclk; 87 struct clk *mclk; 88 struct reset_control *rstc; 89 90 struct completion done; 91 92 const u8 *tx_buf; 93 u8 *rx_buf; 94 int len; 95 unsigned long fifo_depth; 96 }; 97 98 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) 99 { 100 return readl(sspi->base_addr + reg); 101 } 102 103 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) 104 { 105 writel(value, sspi->base_addr + reg); 106 } 107 108 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi) 109 { 110 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 111 112 return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg); 113 } 114 115 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) 116 { 117 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 118 119 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg); 120 } 121 122 static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) 123 { 124 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 125 126 reg |= mask; 127 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 128 } 129 130 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) 131 { 132 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 133 134 reg &= ~mask; 135 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 136 } 137 138 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) 139 { 140 u32 cnt; 141 u8 byte; 142 143 /* See how much data is available */ 144 cnt = sun6i_spi_get_rx_fifo_count(sspi); 145 146 if (len > cnt) 147 len = cnt; 148 149 while (len--) { 150 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); 151 if (sspi->rx_buf) 152 *sspi->rx_buf++ = byte; 153 } 154 } 155 156 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) 157 { 158 u32 cnt; 159 u8 byte; 160 161 /* See how much data we can fit */ 162 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); 163 164 len = min3(len, (int)cnt, sspi->len); 165 166 while (len--) { 167 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; 168 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); 169 sspi->len--; 170 } 171 } 172 173 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) 174 { 175 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); 176 u32 reg; 177 178 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 179 reg &= ~SUN6I_TFR_CTL_CS_MASK; 180 reg |= SUN6I_TFR_CTL_CS(spi->chip_select); 181 182 if (enable) 183 reg |= SUN6I_TFR_CTL_CS_LEVEL; 184 else 185 reg &= ~SUN6I_TFR_CTL_CS_LEVEL; 186 187 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 188 } 189 190 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) 191 { 192 return SUN6I_MAX_XFER_SIZE - 1; 193 } 194 195 static int sun6i_spi_transfer_one(struct spi_master *master, 196 struct spi_device *spi, 197 struct spi_transfer *tfr) 198 { 199 struct sun6i_spi *sspi = spi_master_get_devdata(master); 200 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout; 201 unsigned int start, end, tx_time; 202 unsigned int trig_level; 203 unsigned int tx_len = 0; 204 int ret = 0; 205 u32 reg; 206 207 if (tfr->len > SUN6I_MAX_XFER_SIZE) 208 return -EINVAL; 209 210 reinit_completion(&sspi->done); 211 sspi->tx_buf = tfr->tx_buf; 212 sspi->rx_buf = tfr->rx_buf; 213 sspi->len = tfr->len; 214 215 /* Clear pending interrupts */ 216 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); 217 218 /* Reset FIFO */ 219 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 220 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); 221 222 /* 223 * Setup FIFO interrupt trigger level 224 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded 225 * value used in old generation of Allwinner SPI controller. 226 * (See spi-sun4i.c) 227 */ 228 trig_level = sspi->fifo_depth / 4 * 3; 229 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 230 (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | 231 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS)); 232 233 /* 234 * Setup the transfer control register: Chip Select, 235 * polarities, etc. 236 */ 237 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 238 239 if (spi->mode & SPI_CPOL) 240 reg |= SUN6I_TFR_CTL_CPOL; 241 else 242 reg &= ~SUN6I_TFR_CTL_CPOL; 243 244 if (spi->mode & SPI_CPHA) 245 reg |= SUN6I_TFR_CTL_CPHA; 246 else 247 reg &= ~SUN6I_TFR_CTL_CPHA; 248 249 if (spi->mode & SPI_LSB_FIRST) 250 reg |= SUN6I_TFR_CTL_FBS; 251 else 252 reg &= ~SUN6I_TFR_CTL_FBS; 253 254 /* 255 * If it's a TX only transfer, we don't want to fill the RX 256 * FIFO with bogus data 257 */ 258 if (sspi->rx_buf) 259 reg &= ~SUN6I_TFR_CTL_DHB; 260 else 261 reg |= SUN6I_TFR_CTL_DHB; 262 263 /* We want to control the chip select manually */ 264 reg |= SUN6I_TFR_CTL_CS_MANUAL; 265 266 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 267 268 /* Ensure that we have a parent clock fast enough */ 269 mclk_rate = clk_get_rate(sspi->mclk); 270 if (mclk_rate < (2 * tfr->speed_hz)) { 271 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); 272 mclk_rate = clk_get_rate(sspi->mclk); 273 } 274 275 /* 276 * Setup clock divider. 277 * 278 * We have two choices there. Either we can use the clock 279 * divide rate 1, which is calculated thanks to this formula: 280 * SPI_CLK = MOD_CLK / (2 ^ cdr) 281 * Or we can use CDR2, which is calculated with the formula: 282 * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) 283 * Wether we use the former or the latter is set through the 284 * DRS bit. 285 * 286 * First try CDR2, and if we can't reach the expected 287 * frequency, fall back to CDR1. 288 */ 289 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); 290 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); 291 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { 292 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; 293 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); 294 } else { 295 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); 296 reg = SUN6I_CLK_CTL_CDR1(div); 297 tfr->effective_speed_hz = mclk_rate / (1 << div); 298 } 299 300 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); 301 302 /* Setup the transfer now... */ 303 if (sspi->tx_buf) 304 tx_len = tfr->len; 305 306 /* Setup the counters */ 307 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); 308 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len); 309 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len); 310 311 /* Fill the TX FIFO */ 312 sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); 313 314 /* Enable the interrupts */ 315 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); 316 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC | 317 SUN6I_INT_CTL_RF_RDY); 318 if (tx_len > sspi->fifo_depth) 319 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); 320 321 /* Start the transfer */ 322 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 323 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); 324 325 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); 326 start = jiffies; 327 timeout = wait_for_completion_timeout(&sspi->done, 328 msecs_to_jiffies(tx_time)); 329 end = jiffies; 330 if (!timeout) { 331 dev_warn(&master->dev, 332 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", 333 dev_name(&spi->dev), tfr->len, tfr->speed_hz, 334 jiffies_to_msecs(end - start), tx_time); 335 ret = -ETIMEDOUT; 336 } 337 338 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); 339 340 return ret; 341 } 342 343 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) 344 { 345 struct sun6i_spi *sspi = dev_id; 346 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); 347 348 /* Transfer complete */ 349 if (status & SUN6I_INT_CTL_TC) { 350 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); 351 sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); 352 complete(&sspi->done); 353 return IRQ_HANDLED; 354 } 355 356 /* Receive FIFO 3/4 full */ 357 if (status & SUN6I_INT_CTL_RF_RDY) { 358 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); 359 /* Only clear the interrupt _after_ draining the FIFO */ 360 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY); 361 return IRQ_HANDLED; 362 } 363 364 /* Transmit FIFO 3/4 empty */ 365 if (status & SUN6I_INT_CTL_TF_ERQ) { 366 sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); 367 368 if (!sspi->len) 369 /* nothing left to transmit */ 370 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); 371 372 /* Only clear the interrupt _after_ re-seeding the FIFO */ 373 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ); 374 375 return IRQ_HANDLED; 376 } 377 378 return IRQ_NONE; 379 } 380 381 static int sun6i_spi_runtime_resume(struct device *dev) 382 { 383 struct spi_master *master = dev_get_drvdata(dev); 384 struct sun6i_spi *sspi = spi_master_get_devdata(master); 385 int ret; 386 387 ret = clk_prepare_enable(sspi->hclk); 388 if (ret) { 389 dev_err(dev, "Couldn't enable AHB clock\n"); 390 goto out; 391 } 392 393 ret = clk_prepare_enable(sspi->mclk); 394 if (ret) { 395 dev_err(dev, "Couldn't enable module clock\n"); 396 goto err; 397 } 398 399 ret = reset_control_deassert(sspi->rstc); 400 if (ret) { 401 dev_err(dev, "Couldn't deassert the device from reset\n"); 402 goto err2; 403 } 404 405 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, 406 SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); 407 408 return 0; 409 410 err2: 411 clk_disable_unprepare(sspi->mclk); 412 err: 413 clk_disable_unprepare(sspi->hclk); 414 out: 415 return ret; 416 } 417 418 static int sun6i_spi_runtime_suspend(struct device *dev) 419 { 420 struct spi_master *master = dev_get_drvdata(dev); 421 struct sun6i_spi *sspi = spi_master_get_devdata(master); 422 423 reset_control_assert(sspi->rstc); 424 clk_disable_unprepare(sspi->mclk); 425 clk_disable_unprepare(sspi->hclk); 426 427 return 0; 428 } 429 430 static int sun6i_spi_probe(struct platform_device *pdev) 431 { 432 struct spi_master *master; 433 struct sun6i_spi *sspi; 434 int ret = 0, irq; 435 436 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); 437 if (!master) { 438 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 439 return -ENOMEM; 440 } 441 442 platform_set_drvdata(pdev, master); 443 sspi = spi_master_get_devdata(master); 444 445 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0); 446 if (IS_ERR(sspi->base_addr)) { 447 ret = PTR_ERR(sspi->base_addr); 448 goto err_free_master; 449 } 450 451 irq = platform_get_irq(pdev, 0); 452 if (irq < 0) { 453 ret = -ENXIO; 454 goto err_free_master; 455 } 456 457 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, 458 0, "sun6i-spi", sspi); 459 if (ret) { 460 dev_err(&pdev->dev, "Cannot request IRQ\n"); 461 goto err_free_master; 462 } 463 464 sspi->master = master; 465 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); 466 467 master->max_speed_hz = 100 * 1000 * 1000; 468 master->min_speed_hz = 3 * 1000; 469 master->use_gpio_descriptors = true; 470 master->set_cs = sun6i_spi_set_cs; 471 master->transfer_one = sun6i_spi_transfer_one; 472 master->num_chipselect = 4; 473 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 474 master->bits_per_word_mask = SPI_BPW_MASK(8); 475 master->dev.of_node = pdev->dev.of_node; 476 master->auto_runtime_pm = true; 477 master->max_transfer_size = sun6i_spi_max_transfer_size; 478 479 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 480 if (IS_ERR(sspi->hclk)) { 481 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 482 ret = PTR_ERR(sspi->hclk); 483 goto err_free_master; 484 } 485 486 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); 487 if (IS_ERR(sspi->mclk)) { 488 dev_err(&pdev->dev, "Unable to acquire module clock\n"); 489 ret = PTR_ERR(sspi->mclk); 490 goto err_free_master; 491 } 492 493 init_completion(&sspi->done); 494 495 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 496 if (IS_ERR(sspi->rstc)) { 497 dev_err(&pdev->dev, "Couldn't get reset controller\n"); 498 ret = PTR_ERR(sspi->rstc); 499 goto err_free_master; 500 } 501 502 /* 503 * This wake-up/shutdown pattern is to be able to have the 504 * device woken up, even if runtime_pm is disabled 505 */ 506 ret = sun6i_spi_runtime_resume(&pdev->dev); 507 if (ret) { 508 dev_err(&pdev->dev, "Couldn't resume the device\n"); 509 goto err_free_master; 510 } 511 512 pm_runtime_set_active(&pdev->dev); 513 pm_runtime_enable(&pdev->dev); 514 pm_runtime_idle(&pdev->dev); 515 516 ret = devm_spi_register_master(&pdev->dev, master); 517 if (ret) { 518 dev_err(&pdev->dev, "cannot register SPI master\n"); 519 goto err_pm_disable; 520 } 521 522 return 0; 523 524 err_pm_disable: 525 pm_runtime_disable(&pdev->dev); 526 sun6i_spi_runtime_suspend(&pdev->dev); 527 err_free_master: 528 spi_master_put(master); 529 return ret; 530 } 531 532 static int sun6i_spi_remove(struct platform_device *pdev) 533 { 534 pm_runtime_force_suspend(&pdev->dev); 535 536 return 0; 537 } 538 539 static const struct of_device_id sun6i_spi_match[] = { 540 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, 541 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, 542 {} 543 }; 544 MODULE_DEVICE_TABLE(of, sun6i_spi_match); 545 546 static const struct dev_pm_ops sun6i_spi_pm_ops = { 547 .runtime_resume = sun6i_spi_runtime_resume, 548 .runtime_suspend = sun6i_spi_runtime_suspend, 549 }; 550 551 static struct platform_driver sun6i_spi_driver = { 552 .probe = sun6i_spi_probe, 553 .remove = sun6i_spi_remove, 554 .driver = { 555 .name = "sun6i-spi", 556 .of_match_table = sun6i_spi_match, 557 .pm = &sun6i_spi_pm_ops, 558 }, 559 }; 560 module_platform_driver(sun6i_spi_driver); 561 562 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); 563 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 564 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); 565 MODULE_LICENSE("GPL"); 566