ksz8795.c (7fcb820c7609f207cd2e5b49bff96a5b55167cf3) ksz8795.c (486f9ca715d7b70ed79dbe91296b9e0110deaab5)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8

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21#include <net/dsa.h>
22#include <net/switchdev.h>
23#include <linux/phylink.h>
24
25#include "ksz_common.h"
26#include "ksz8795_reg.h"
27#include "ksz8.h"
28
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8

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21#include <net/dsa.h>
22#include <net/switchdev.h>
23#include <linux/phylink.h>
24
25#include "ksz_common.h"
26#include "ksz8795_reg.h"
27#include "ksz8.h"
28
29static const u8 ksz8795_regs[] = {
30 [REG_IND_CTRL_0] = 0x6E,
31 [REG_IND_DATA_8] = 0x70,
32 [REG_IND_DATA_CHECK] = 0x72,
33 [REG_IND_DATA_HI] = 0x71,
34 [REG_IND_DATA_LO] = 0x75,
35 [REG_IND_MIB_CHECK] = 0x74,
36 [REG_IND_BYTE] = 0xA0,
37 [P_FORCE_CTRL] = 0x0C,
38 [P_LINK_STATUS] = 0x0E,
39 [P_LOCAL_CTRL] = 0x07,
40 [P_NEG_RESTART_CTRL] = 0x0D,
41 [P_REMOTE_STATUS] = 0x08,
42 [P_SPEED_STATUS] = 0x09,
43 [S_TAIL_TAG_CTRL] = 0x0C,
44};
45
46static const u32 ksz8795_masks[] = {
47 [PORT_802_1P_REMAPPING] = BIT(7),
48 [SW_TAIL_TAG_ENABLE] = BIT(1),
49 [MIB_COUNTER_OVERFLOW] = BIT(6),
50 [MIB_COUNTER_VALID] = BIT(5),
51 [VLAN_TABLE_FID] = GENMASK(6, 0),
52 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
53 [VLAN_TABLE_VALID] = BIT(12),

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72 [STATIC_MAC_FID] = 24,
73 [DYNAMIC_MAC_ENTRIES_H] = 3,
74 [DYNAMIC_MAC_ENTRIES] = 29,
75 [DYNAMIC_MAC_FID] = 16,
76 [DYNAMIC_MAC_TIMESTAMP] = 27,
77 [DYNAMIC_MAC_SRC_PORT] = 24,
78};
79
29static const u32 ksz8795_masks[] = {
30 [PORT_802_1P_REMAPPING] = BIT(7),
31 [SW_TAIL_TAG_ENABLE] = BIT(1),
32 [MIB_COUNTER_OVERFLOW] = BIT(6),
33 [MIB_COUNTER_VALID] = BIT(5),
34 [VLAN_TABLE_FID] = GENMASK(6, 0),
35 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
36 [VLAN_TABLE_VALID] = BIT(12),

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55 [STATIC_MAC_FID] = 24,
56 [DYNAMIC_MAC_ENTRIES_H] = 3,
57 [DYNAMIC_MAC_ENTRIES] = 29,
58 [DYNAMIC_MAC_FID] = 16,
59 [DYNAMIC_MAC_TIMESTAMP] = 27,
60 [DYNAMIC_MAC_SRC_PORT] = 24,
61};
62
80static const u8 ksz8863_regs[] = {
81 [REG_IND_CTRL_0] = 0x79,
82 [REG_IND_DATA_8] = 0x7B,
83 [REG_IND_DATA_CHECK] = 0x7B,
84 [REG_IND_DATA_HI] = 0x7C,
85 [REG_IND_DATA_LO] = 0x80,
86 [REG_IND_MIB_CHECK] = 0x80,
87 [P_FORCE_CTRL] = 0x0C,
88 [P_LINK_STATUS] = 0x0E,
89 [P_LOCAL_CTRL] = 0x0C,
90 [P_NEG_RESTART_CTRL] = 0x0D,
91 [P_REMOTE_STATUS] = 0x0E,
92 [P_SPEED_STATUS] = 0x0F,
93 [S_TAIL_TAG_CTRL] = 0x03,
94};
95
96static const u32 ksz8863_masks[] = {
97 [PORT_802_1P_REMAPPING] = BIT(3),
98 [SW_TAIL_TAG_ENABLE] = BIT(6),
99 [MIB_COUNTER_OVERFLOW] = BIT(7),
100 [MIB_COUNTER_VALID] = BIT(6),
101 [VLAN_TABLE_FID] = GENMASK(15, 12),
102 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
103 [VLAN_TABLE_VALID] = BIT(19),

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140 bool set)
141{
142 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
143 bits, set ? bits : 0);
144}
145
146static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data)
147{
63static const u32 ksz8863_masks[] = {
64 [PORT_802_1P_REMAPPING] = BIT(3),
65 [SW_TAIL_TAG_ENABLE] = BIT(6),
66 [MIB_COUNTER_OVERFLOW] = BIT(7),
67 [MIB_COUNTER_VALID] = BIT(6),
68 [VLAN_TABLE_FID] = GENMASK(15, 12),
69 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
70 [VLAN_TABLE_VALID] = BIT(19),

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107 bool set)
108{
109 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
110 bits, set ? bits : 0);
111}
112
113static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data)
114{
148 struct ksz8 *ksz8 = dev->priv;
149 const u8 *regs = ksz8->regs;
115 const u8 *regs;
150 u16 ctrl_addr;
151 int ret = 0;
152
116 u16 ctrl_addr;
117 int ret = 0;
118
119 regs = dev->info->regs;
120
153 mutex_lock(&dev->alu_mutex);
154
155 ctrl_addr = IND_ACC_TABLE(table) | addr;
156 ret = ksz_write8(dev, regs[REG_IND_BYTE], data);
157 if (!ret)
158 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
159
160 mutex_unlock(&dev->alu_mutex);

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219 const u32 *masks;
220 const u8 *regs;
221 u16 ctrl_addr;
222 u32 data;
223 u8 check;
224 int loop;
225
226 masks = ksz8->masks;
121 mutex_lock(&dev->alu_mutex);
122
123 ctrl_addr = IND_ACC_TABLE(table) | addr;
124 ret = ksz_write8(dev, regs[REG_IND_BYTE], data);
125 if (!ret)
126 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
127
128 mutex_unlock(&dev->alu_mutex);

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187 const u32 *masks;
188 const u8 *regs;
189 u16 ctrl_addr;
190 u32 data;
191 u8 check;
192 int loop;
193
194 masks = ksz8->masks;
227 regs = ksz8->regs;
195 regs = dev->info->regs;
228
229 ctrl_addr = addr + dev->info->reg_mib_cnt * port;
230 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
231
232 mutex_lock(&dev->alu_mutex);
233 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
234
235 /* It is almost guaranteed to always read the valid bit because of

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256 const u32 *masks;
257 const u8 *regs;
258 u16 ctrl_addr;
259 u32 data;
260 u8 check;
261 int loop;
262
263 masks = ksz8->masks;
196
197 ctrl_addr = addr + dev->info->reg_mib_cnt * port;
198 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
199
200 mutex_lock(&dev->alu_mutex);
201 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
202
203 /* It is almost guaranteed to always read the valid bit because of

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224 const u32 *masks;
225 const u8 *regs;
226 u16 ctrl_addr;
227 u32 data;
228 u8 check;
229 int loop;
230
231 masks = ksz8->masks;
264 regs = ksz8->regs;
232 regs = dev->info->regs;
265
266 addr -= dev->info->reg_mib_cnt;
267 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
268 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
269 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
270
271 mutex_lock(&dev->alu_mutex);
272 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);

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300 }
301 }
302 mutex_unlock(&dev->alu_mutex);
303}
304
305static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
306 u64 *dropped, u64 *cnt)
307{
233
234 addr -= dev->info->reg_mib_cnt;
235 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
236 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
237 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
238
239 mutex_lock(&dev->alu_mutex);
240 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);

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268 }
269 }
270 mutex_unlock(&dev->alu_mutex);
271}
272
273static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
274 u64 *dropped, u64 *cnt)
275{
308 struct ksz8 *ksz8 = dev->priv;
309 const u8 *regs = ksz8->regs;
310 u32 *last = (u32 *)dropped;
276 u32 *last = (u32 *)dropped;
277 const u8 *regs;
311 u16 ctrl_addr;
312 u32 data;
313 u32 cur;
314
278 u16 ctrl_addr;
279 u32 data;
280 u32 cur;
281
282 regs = dev->info->regs;
283
315 addr -= dev->info->reg_mib_cnt;
316 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
317 KSZ8863_MIB_PACKET_DROPPED_RX_0;
318 ctrl_addr += port;
319 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
320
321 mutex_lock(&dev->alu_mutex);
322 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);

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387 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
388 dropped, &mib->counters[mib->cnt_ptr]);
389 ++mib->cnt_ptr;
390 }
391}
392
393static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
394{
284 addr -= dev->info->reg_mib_cnt;
285 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
286 KSZ8863_MIB_PACKET_DROPPED_RX_0;
287 ctrl_addr += port;
288 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
289
290 mutex_lock(&dev->alu_mutex);
291 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);

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356 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
357 dropped, &mib->counters[mib->cnt_ptr]);
358 ++mib->cnt_ptr;
359 }
360}
361
362static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
363{
395 struct ksz8 *ksz8 = dev->priv;
396 const u8 *regs = ksz8->regs;
364 const u8 *regs;
397 u16 ctrl_addr;
398
365 u16 ctrl_addr;
366
367 regs = dev->info->regs;
368
399 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
400
401 mutex_lock(&dev->alu_mutex);
402 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
403 ksz_read64(dev, regs[REG_IND_DATA_HI], data);
404 mutex_unlock(&dev->alu_mutex);
405}
406
407static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
408{
369 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
370
371 mutex_lock(&dev->alu_mutex);
372 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
373 ksz_read64(dev, regs[REG_IND_DATA_HI], data);
374 mutex_unlock(&dev->alu_mutex);
375}
376
377static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
378{
409 struct ksz8 *ksz8 = dev->priv;
410 const u8 *regs = ksz8->regs;
379 const u8 *regs;
411 u16 ctrl_addr;
412
380 u16 ctrl_addr;
381
382 regs = dev->info->regs;
383
413 ctrl_addr = IND_ACC_TABLE(table) | addr;
414
415 mutex_lock(&dev->alu_mutex);
416 ksz_write64(dev, regs[REG_IND_DATA_HI], data);
417 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
418 mutex_unlock(&dev->alu_mutex);
419}
420
421static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
422{
423 struct ksz8 *ksz8 = dev->priv;
424 int timeout = 100;
425 const u32 *masks;
426 const u8 *regs;
427
428 masks = ksz8->masks;
384 ctrl_addr = IND_ACC_TABLE(table) | addr;
385
386 mutex_lock(&dev->alu_mutex);
387 ksz_write64(dev, regs[REG_IND_DATA_HI], data);
388 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
389 mutex_unlock(&dev->alu_mutex);
390}
391
392static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
393{
394 struct ksz8 *ksz8 = dev->priv;
395 int timeout = 100;
396 const u32 *masks;
397 const u8 *regs;
398
399 masks = ksz8->masks;
429 regs = ksz8->regs;
400 regs = dev->info->regs;
430
431 do {
432 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
433 timeout--;
434 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
435
436 /* Entry is not ready for accessing. */
437 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) {

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456 const u32 *masks;
457 const u8 *regs;
458 u16 ctrl_addr;
459 u8 data;
460 int rc;
461
462 shifts = ksz8->shifts;
463 masks = ksz8->masks;
401
402 do {
403 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
404 timeout--;
405 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
406
407 /* Entry is not ready for accessing. */
408 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) {

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427 const u32 *masks;
428 const u8 *regs;
429 u16 ctrl_addr;
430 u8 data;
431 int rc;
432
433 shifts = ksz8->shifts;
434 masks = ksz8->masks;
464 regs = ksz8->regs;
435 regs = dev->info->regs;
465
466 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
467
468 mutex_lock(&dev->alu_mutex);
469 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
470
471 rc = ksz8_valid_dyn_entry(dev, &data);
472 if (rc == -EAGAIN) {

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659 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
660 data[index] = vlan;
661 dev->vlan_cache[vid].table[0] = vlan;
662 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
663}
664
665void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
666{
436
437 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
438
439 mutex_lock(&dev->alu_mutex);
440 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
441
442 rc = ksz8_valid_dyn_entry(dev, &data);
443 if (rc == -EAGAIN) {

--- 186 unchanged lines hidden (view full) ---

630 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
631 data[index] = vlan;
632 dev->vlan_cache[vid].table[0] = vlan;
633 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
634}
635
636void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
637{
667 struct ksz8 *ksz8 = dev->priv;
668 u8 restart, speed, ctrl, link;
638 u8 restart, speed, ctrl, link;
669 const u8 *regs = ksz8->regs;
670 int processed = true;
639 int processed = true;
640 const u8 *regs;
671 u8 val1, val2;
672 u16 data = 0;
673 u8 p = phy;
674
641 u8 val1, val2;
642 u16 data = 0;
643 u8 p = phy;
644
645 regs = dev->info->regs;
646
675 switch (reg) {
676 case MII_BMCR:
677 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
678 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
679 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
680 if (restart & PORT_PHY_LOOPBACK)
681 data |= BMCR_LOOPBACK;
682 if (ctrl & PORT_FORCE_100_MBIT)

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782 break;
783 }
784 if (processed)
785 *val = data;
786}
787
788void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
789{
647 switch (reg) {
648 case MII_BMCR:
649 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
650 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
651 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
652 if (restart & PORT_PHY_LOOPBACK)
653 data |= BMCR_LOOPBACK;
654 if (ctrl & PORT_FORCE_100_MBIT)

--- 99 unchanged lines hidden (view full) ---

754 break;
755 }
756 if (processed)
757 *val = data;
758}
759
760void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
761{
790 struct ksz8 *ksz8 = dev->priv;
791 u8 restart, speed, ctrl, data;
762 u8 restart, speed, ctrl, data;
792 const u8 *regs = ksz8->regs;
763 const u8 *regs;
793 u8 p = phy;
794
764 u8 p = phy;
765
766 regs = dev->info->regs;
767
795 switch (reg) {
796 case MII_BMCR:
797
798 /* Do not support PHY reset function. */
799 if (val & BMCR_RESET)
800 break;
801 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
802 data = speed;

--- 494 unchanged lines hidden (view full) ---

1297
1298 ksz8_cfg_port_member(dev, port, member);
1299}
1300
1301void ksz8_config_cpu_port(struct dsa_switch *ds)
1302{
1303 struct ksz_device *dev = ds->priv;
1304 struct ksz8 *ksz8 = dev->priv;
768 switch (reg) {
769 case MII_BMCR:
770
771 /* Do not support PHY reset function. */
772 if (val & BMCR_RESET)
773 break;
774 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
775 data = speed;

--- 494 unchanged lines hidden (view full) ---

1270
1271 ksz8_cfg_port_member(dev, port, member);
1272}
1273
1274void ksz8_config_cpu_port(struct dsa_switch *ds)
1275{
1276 struct ksz_device *dev = ds->priv;
1277 struct ksz8 *ksz8 = dev->priv;
1305 const u8 *regs = ksz8->regs;
1306 struct ksz_port *p;
1307 const u32 *masks;
1278 struct ksz_port *p;
1279 const u32 *masks;
1280 const u8 *regs;
1308 u8 remote;
1309 int i;
1310
1311 masks = ksz8->masks;
1281 u8 remote;
1282 int i;
1283
1284 masks = ksz8->masks;
1285 regs = dev->info->regs;
1312
1313 /* Switch marks the maximum frame with extra byte as oversize. */
1314 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
1315 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1316
1317 p = &dev->ports[dev->cpu_port];
1318 p->on = 1;
1319

--- 123 unchanged lines hidden (view full) ---

1443{
1444 struct ksz8 *ksz8 = dev->priv;
1445
1446 dev->cpu_port = fls(dev->info->cpu_ports) - 1;
1447 dev->phy_port_cnt = dev->info->port_cnt - 1;
1448 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports;
1449
1450 if (ksz_is_ksz88x3(dev)) {
1286
1287 /* Switch marks the maximum frame with extra byte as oversize. */
1288 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
1289 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1290
1291 p = &dev->ports[dev->cpu_port];
1292 p->on = 1;
1293

--- 123 unchanged lines hidden (view full) ---

1417{
1418 struct ksz8 *ksz8 = dev->priv;
1419
1420 dev->cpu_port = fls(dev->info->cpu_ports) - 1;
1421 dev->phy_port_cnt = dev->info->port_cnt - 1;
1422 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports;
1423
1424 if (ksz_is_ksz88x3(dev)) {
1451 ksz8->regs = ksz8863_regs;
1452 ksz8->masks = ksz8863_masks;
1453 ksz8->shifts = ksz8863_shifts;
1454 } else {
1425 ksz8->masks = ksz8863_masks;
1426 ksz8->shifts = ksz8863_shifts;
1427 } else {
1455 ksz8->regs = ksz8795_regs;
1456 ksz8->masks = ksz8795_masks;
1457 ksz8->shifts = ksz8795_shifts;
1458 }
1459
1460 /* We rely on software untagging on the CPU port, so that we
1461 * can support both tagged and untagged VLANs
1462 */
1463 dev->ds->untag_bridge_pvid = true;

--- 17 unchanged lines hidden --- 		1428 ksz8->masks = ksz8795_masks;
1429 ksz8->shifts = ksz8795_shifts;
1430 }
1431
1432 /* We rely on software untagging on the CPU port, so that we
1433 * can support both tagged and untagged VLANs
1434 */
1435 dev->ds->untag_bridge_pvid = true;

--- 17 unchanged lines hidden ---