1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8795 switch driver 4 * 5 * Copyright (C) 2017 Microchip Technology Inc. 6 * Tristram Ha <Tristram.Ha@microchip.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/gpio.h> 13 #include <linux/if_vlan.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_data/microchip-ksz.h> 17 #include <linux/phy.h> 18 #include <linux/etherdevice.h> 19 #include <linux/if_bridge.h> 20 #include <linux/micrel_phy.h> 21 #include <net/dsa.h> 22 #include <net/switchdev.h> 23 #include <linux/phylink.h> 24 25 #include "ksz_common.h" 26 #include "ksz8795_reg.h" 27 #include "ksz8.h" 28 29 static const u32 ksz8795_masks[] = { 30 [PORT_802_1P_REMAPPING] = BIT(7), 31 [SW_TAIL_TAG_ENABLE] = BIT(1), 32 [MIB_COUNTER_OVERFLOW] = BIT(6), 33 [MIB_COUNTER_VALID] = BIT(5), 34 [VLAN_TABLE_FID] = GENMASK(6, 0), 35 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 36 [VLAN_TABLE_VALID] = BIT(12), 37 [STATIC_MAC_TABLE_VALID] = BIT(21), 38 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 39 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 40 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 41 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 42 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 43 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 44 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 45 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 46 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 47 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 48 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 49 }; 50 51 static const u8 ksz8795_shifts[] = { 52 [VLAN_TABLE_MEMBERSHIP_S] = 7, 53 [VLAN_TABLE] = 16, 54 [STATIC_MAC_FWD_PORTS] = 16, 55 [STATIC_MAC_FID] = 24, 56 [DYNAMIC_MAC_ENTRIES_H] = 3, 57 [DYNAMIC_MAC_ENTRIES] = 29, 58 [DYNAMIC_MAC_FID] = 16, 59 [DYNAMIC_MAC_TIMESTAMP] = 27, 60 [DYNAMIC_MAC_SRC_PORT] = 24, 61 }; 62 63 static const u32 ksz8863_masks[] = { 64 [PORT_802_1P_REMAPPING] = BIT(3), 65 [SW_TAIL_TAG_ENABLE] = BIT(6), 66 [MIB_COUNTER_OVERFLOW] = BIT(7), 67 [MIB_COUNTER_VALID] = BIT(6), 68 [VLAN_TABLE_FID] = GENMASK(15, 12), 69 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 70 [VLAN_TABLE_VALID] = BIT(19), 71 [STATIC_MAC_TABLE_VALID] = BIT(19), 72 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 73 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 74 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 75 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 76 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 77 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 78 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 79 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 80 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 81 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 82 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 83 }; 84 85 static u8 ksz8863_shifts[] = { 86 [VLAN_TABLE_MEMBERSHIP_S] = 16, 87 [STATIC_MAC_FWD_PORTS] = 16, 88 [STATIC_MAC_FID] = 22, 89 [DYNAMIC_MAC_ENTRIES_H] = 3, 90 [DYNAMIC_MAC_ENTRIES] = 24, 91 [DYNAMIC_MAC_FID] = 16, 92 [DYNAMIC_MAC_TIMESTAMP] = 24, 93 [DYNAMIC_MAC_SRC_PORT] = 20, 94 }; 95 96 static bool ksz_is_ksz88x3(struct ksz_device *dev) 97 { 98 return dev->chip_id == 0x8830; 99 } 100 101 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 102 { 103 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 104 } 105 106 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 107 bool set) 108 { 109 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 110 bits, set ? bits : 0); 111 } 112 113 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 114 { 115 const u8 *regs; 116 u16 ctrl_addr; 117 int ret = 0; 118 119 regs = dev->info->regs; 120 121 mutex_lock(&dev->alu_mutex); 122 123 ctrl_addr = IND_ACC_TABLE(table) | addr; 124 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 125 if (!ret) 126 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 127 128 mutex_unlock(&dev->alu_mutex); 129 130 return ret; 131 } 132 133 int ksz8_reset_switch(struct ksz_device *dev) 134 { 135 if (ksz_is_ksz88x3(dev)) { 136 /* reset switch */ 137 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 138 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 139 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 140 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 141 } else { 142 /* reset switch */ 143 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 144 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 145 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 146 } 147 148 return 0; 149 } 150 151 static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue) 152 { 153 u8 hi, lo; 154 155 /* Number of queues can only be 1, 2, or 4. */ 156 switch (queue) { 157 case 4: 158 case 3: 159 queue = PORT_QUEUE_SPLIT_4; 160 break; 161 case 2: 162 queue = PORT_QUEUE_SPLIT_2; 163 break; 164 default: 165 queue = PORT_QUEUE_SPLIT_1; 166 } 167 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo); 168 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi); 169 lo &= ~PORT_QUEUE_SPLIT_L; 170 if (queue & PORT_QUEUE_SPLIT_2) 171 lo |= PORT_QUEUE_SPLIT_L; 172 hi &= ~PORT_QUEUE_SPLIT_H; 173 if (queue & PORT_QUEUE_SPLIT_4) 174 hi |= PORT_QUEUE_SPLIT_H; 175 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo); 176 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi); 177 178 /* Default is port based for egress rate limit. */ 179 if (queue != PORT_QUEUE_SPLIT_1) 180 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED, 181 true); 182 } 183 184 void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 185 { 186 struct ksz8 *ksz8 = dev->priv; 187 const u32 *masks; 188 const u8 *regs; 189 u16 ctrl_addr; 190 u32 data; 191 u8 check; 192 int loop; 193 194 masks = ksz8->masks; 195 regs = dev->info->regs; 196 197 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 198 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 199 200 mutex_lock(&dev->alu_mutex); 201 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 202 203 /* It is almost guaranteed to always read the valid bit because of 204 * slow SPI speed. 205 */ 206 for (loop = 2; loop > 0; loop--) { 207 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 208 209 if (check & masks[MIB_COUNTER_VALID]) { 210 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 211 if (check & masks[MIB_COUNTER_OVERFLOW]) 212 *cnt += MIB_COUNTER_VALUE + 1; 213 *cnt += data & MIB_COUNTER_VALUE; 214 break; 215 } 216 } 217 mutex_unlock(&dev->alu_mutex); 218 } 219 220 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 221 u64 *dropped, u64 *cnt) 222 { 223 struct ksz8 *ksz8 = dev->priv; 224 const u32 *masks; 225 const u8 *regs; 226 u16 ctrl_addr; 227 u32 data; 228 u8 check; 229 int loop; 230 231 masks = ksz8->masks; 232 regs = dev->info->regs; 233 234 addr -= dev->info->reg_mib_cnt; 235 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 236 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 237 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 238 239 mutex_lock(&dev->alu_mutex); 240 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 241 242 /* It is almost guaranteed to always read the valid bit because of 243 * slow SPI speed. 244 */ 245 for (loop = 2; loop > 0; loop--) { 246 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 247 248 if (check & masks[MIB_COUNTER_VALID]) { 249 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 250 if (addr < 2) { 251 u64 total; 252 253 total = check & MIB_TOTAL_BYTES_H; 254 total <<= 32; 255 *cnt += total; 256 *cnt += data; 257 if (check & masks[MIB_COUNTER_OVERFLOW]) { 258 total = MIB_TOTAL_BYTES_H + 1; 259 total <<= 32; 260 *cnt += total; 261 } 262 } else { 263 if (check & masks[MIB_COUNTER_OVERFLOW]) 264 *cnt += MIB_PACKET_DROPPED + 1; 265 *cnt += data & MIB_PACKET_DROPPED; 266 } 267 break; 268 } 269 } 270 mutex_unlock(&dev->alu_mutex); 271 } 272 273 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 274 u64 *dropped, u64 *cnt) 275 { 276 u32 *last = (u32 *)dropped; 277 const u8 *regs; 278 u16 ctrl_addr; 279 u32 data; 280 u32 cur; 281 282 regs = dev->info->regs; 283 284 addr -= dev->info->reg_mib_cnt; 285 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 286 KSZ8863_MIB_PACKET_DROPPED_RX_0; 287 ctrl_addr += port; 288 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 289 290 mutex_lock(&dev->alu_mutex); 291 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 292 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 293 mutex_unlock(&dev->alu_mutex); 294 295 data &= MIB_PACKET_DROPPED; 296 cur = last[addr]; 297 if (data != cur) { 298 last[addr] = data; 299 if (data < cur) 300 data += MIB_PACKET_DROPPED + 1; 301 data -= cur; 302 *cnt += data; 303 } 304 } 305 306 void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 307 u64 *dropped, u64 *cnt) 308 { 309 if (ksz_is_ksz88x3(dev)) 310 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 311 else 312 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 313 } 314 315 void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 316 { 317 if (ksz_is_ksz88x3(dev)) 318 return; 319 320 /* enable the port for flush/freeze function */ 321 if (freeze) 322 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 323 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 324 325 /* disable the port after freeze is done */ 326 if (!freeze) 327 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 328 } 329 330 void ksz8_port_init_cnt(struct ksz_device *dev, int port) 331 { 332 struct ksz_port_mib *mib = &dev->ports[port].mib; 333 u64 *dropped; 334 335 if (!ksz_is_ksz88x3(dev)) { 336 /* flush all enabled port MIB counters */ 337 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 338 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 339 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 340 } 341 342 mib->cnt_ptr = 0; 343 344 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 345 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 346 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 347 &mib->counters[mib->cnt_ptr]); 348 ++mib->cnt_ptr; 349 } 350 351 /* last one in storage */ 352 dropped = &mib->counters[dev->info->mib_cnt]; 353 354 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 355 while (mib->cnt_ptr < dev->info->mib_cnt) { 356 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 357 dropped, &mib->counters[mib->cnt_ptr]); 358 ++mib->cnt_ptr; 359 } 360 } 361 362 static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 363 { 364 const u8 *regs; 365 u16 ctrl_addr; 366 367 regs = dev->info->regs; 368 369 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 370 371 mutex_lock(&dev->alu_mutex); 372 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 373 ksz_read64(dev, regs[REG_IND_DATA_HI], data); 374 mutex_unlock(&dev->alu_mutex); 375 } 376 377 static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 378 { 379 const u8 *regs; 380 u16 ctrl_addr; 381 382 regs = dev->info->regs; 383 384 ctrl_addr = IND_ACC_TABLE(table) | addr; 385 386 mutex_lock(&dev->alu_mutex); 387 ksz_write64(dev, regs[REG_IND_DATA_HI], data); 388 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 389 mutex_unlock(&dev->alu_mutex); 390 } 391 392 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 393 { 394 struct ksz8 *ksz8 = dev->priv; 395 int timeout = 100; 396 const u32 *masks; 397 const u8 *regs; 398 399 masks = ksz8->masks; 400 regs = dev->info->regs; 401 402 do { 403 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 404 timeout--; 405 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 406 407 /* Entry is not ready for accessing. */ 408 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) { 409 return -EAGAIN; 410 /* Entry is ready for accessing. */ 411 } else { 412 ksz_read8(dev, regs[REG_IND_DATA_8], data); 413 414 /* There is no valid entry in the table. */ 415 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) 416 return -ENXIO; 417 } 418 return 0; 419 } 420 421 int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr, 422 u8 *fid, u8 *src_port, u8 *timestamp, u16 *entries) 423 { 424 struct ksz8 *ksz8 = dev->priv; 425 u32 data_hi, data_lo; 426 const u8 *shifts; 427 const u32 *masks; 428 const u8 *regs; 429 u16 ctrl_addr; 430 u8 data; 431 int rc; 432 433 shifts = ksz8->shifts; 434 masks = ksz8->masks; 435 regs = dev->info->regs; 436 437 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 438 439 mutex_lock(&dev->alu_mutex); 440 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 441 442 rc = ksz8_valid_dyn_entry(dev, &data); 443 if (rc == -EAGAIN) { 444 if (addr == 0) 445 *entries = 0; 446 } else if (rc == -ENXIO) { 447 *entries = 0; 448 /* At least one valid entry in the table. */ 449 } else { 450 u64 buf = 0; 451 int cnt; 452 453 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 454 data_hi = (u32)(buf >> 32); 455 data_lo = (u32)buf; 456 457 /* Check out how many valid entry in the table. */ 458 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 459 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 460 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 461 shifts[DYNAMIC_MAC_ENTRIES]; 462 *entries = cnt + 1; 463 464 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 465 shifts[DYNAMIC_MAC_FID]; 466 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 467 shifts[DYNAMIC_MAC_SRC_PORT]; 468 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >> 469 shifts[DYNAMIC_MAC_TIMESTAMP]; 470 471 mac_addr[5] = (u8)data_lo; 472 mac_addr[4] = (u8)(data_lo >> 8); 473 mac_addr[3] = (u8)(data_lo >> 16); 474 mac_addr[2] = (u8)(data_lo >> 24); 475 476 mac_addr[1] = (u8)data_hi; 477 mac_addr[0] = (u8)(data_hi >> 8); 478 rc = 0; 479 } 480 mutex_unlock(&dev->alu_mutex); 481 482 return rc; 483 } 484 485 int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 486 struct alu_struct *alu) 487 { 488 struct ksz8 *ksz8 = dev->priv; 489 u32 data_hi, data_lo; 490 const u8 *shifts; 491 const u32 *masks; 492 u64 data; 493 494 shifts = ksz8->shifts; 495 masks = ksz8->masks; 496 497 ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 498 data_hi = data >> 32; 499 data_lo = (u32)data; 500 if (data_hi & (masks[STATIC_MAC_TABLE_VALID] | 501 masks[STATIC_MAC_TABLE_OVERRIDE])) { 502 alu->mac[5] = (u8)data_lo; 503 alu->mac[4] = (u8)(data_lo >> 8); 504 alu->mac[3] = (u8)(data_lo >> 16); 505 alu->mac[2] = (u8)(data_lo >> 24); 506 alu->mac[1] = (u8)data_hi; 507 alu->mac[0] = (u8)(data_hi >> 8); 508 alu->port_forward = 509 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 510 shifts[STATIC_MAC_FWD_PORTS]; 511 alu->is_override = 512 (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 513 data_hi >>= 1; 514 alu->is_static = true; 515 alu->is_use_fid = 516 (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 517 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 518 shifts[STATIC_MAC_FID]; 519 return 0; 520 } 521 return -ENXIO; 522 } 523 524 void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 525 struct alu_struct *alu) 526 { 527 struct ksz8 *ksz8 = dev->priv; 528 u32 data_hi, data_lo; 529 const u8 *shifts; 530 const u32 *masks; 531 u64 data; 532 533 shifts = ksz8->shifts; 534 masks = ksz8->masks; 535 536 data_lo = ((u32)alu->mac[2] << 24) | 537 ((u32)alu->mac[3] << 16) | 538 ((u32)alu->mac[4] << 8) | alu->mac[5]; 539 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 540 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 541 542 if (alu->is_override) 543 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 544 if (alu->is_use_fid) { 545 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 546 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 547 } 548 if (alu->is_static) 549 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 550 else 551 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 552 553 data = (u64)data_hi << 32 | data_lo; 554 ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 555 } 556 557 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 558 u8 *member, u8 *valid) 559 { 560 struct ksz8 *ksz8 = dev->priv; 561 const u8 *shifts; 562 const u32 *masks; 563 564 shifts = ksz8->shifts; 565 masks = ksz8->masks; 566 567 *fid = vlan & masks[VLAN_TABLE_FID]; 568 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 569 shifts[VLAN_TABLE_MEMBERSHIP_S]; 570 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 571 } 572 573 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 574 u16 *vlan) 575 { 576 struct ksz8 *ksz8 = dev->priv; 577 const u8 *shifts; 578 const u32 *masks; 579 580 shifts = ksz8->shifts; 581 masks = ksz8->masks; 582 583 *vlan = fid; 584 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 585 if (valid) 586 *vlan |= masks[VLAN_TABLE_VALID]; 587 } 588 589 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 590 { 591 struct ksz8 *ksz8 = dev->priv; 592 const u8 *shifts; 593 u64 data; 594 int i; 595 596 shifts = ksz8->shifts; 597 598 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 599 addr *= 4; 600 for (i = 0; i < 4; i++) { 601 dev->vlan_cache[addr + i].table[0] = (u16)data; 602 data >>= shifts[VLAN_TABLE]; 603 } 604 } 605 606 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 607 { 608 int index; 609 u16 *data; 610 u16 addr; 611 u64 buf; 612 613 data = (u16 *)&buf; 614 addr = vid / 4; 615 index = vid & 3; 616 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 617 *vlan = data[index]; 618 } 619 620 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 621 { 622 int index; 623 u16 *data; 624 u16 addr; 625 u64 buf; 626 627 data = (u16 *)&buf; 628 addr = vid / 4; 629 index = vid & 3; 630 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 631 data[index] = vlan; 632 dev->vlan_cache[vid].table[0] = vlan; 633 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 634 } 635 636 void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 637 { 638 u8 restart, speed, ctrl, link; 639 int processed = true; 640 const u8 *regs; 641 u8 val1, val2; 642 u16 data = 0; 643 u8 p = phy; 644 645 regs = dev->info->regs; 646 647 switch (reg) { 648 case MII_BMCR: 649 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 650 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 651 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 652 if (restart & PORT_PHY_LOOPBACK) 653 data |= BMCR_LOOPBACK; 654 if (ctrl & PORT_FORCE_100_MBIT) 655 data |= BMCR_SPEED100; 656 if (ksz_is_ksz88x3(dev)) { 657 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 658 data |= BMCR_ANENABLE; 659 } else { 660 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 661 data |= BMCR_ANENABLE; 662 } 663 if (restart & PORT_POWER_DOWN) 664 data |= BMCR_PDOWN; 665 if (restart & PORT_AUTO_NEG_RESTART) 666 data |= BMCR_ANRESTART; 667 if (ctrl & PORT_FORCE_FULL_DUPLEX) 668 data |= BMCR_FULLDPLX; 669 if (speed & PORT_HP_MDIX) 670 data |= KSZ886X_BMCR_HP_MDIX; 671 if (restart & PORT_FORCE_MDIX) 672 data |= KSZ886X_BMCR_FORCE_MDI; 673 if (restart & PORT_AUTO_MDIX_DISABLE) 674 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 675 if (restart & PORT_TX_DISABLE) 676 data |= KSZ886X_BMCR_DISABLE_TRANSMIT; 677 if (restart & PORT_LED_OFF) 678 data |= KSZ886X_BMCR_DISABLE_LED; 679 break; 680 case MII_BMSR: 681 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 682 data = BMSR_100FULL | 683 BMSR_100HALF | 684 BMSR_10FULL | 685 BMSR_10HALF | 686 BMSR_ANEGCAPABLE; 687 if (link & PORT_AUTO_NEG_COMPLETE) 688 data |= BMSR_ANEGCOMPLETE; 689 if (link & PORT_STAT_LINK_GOOD) 690 data |= BMSR_LSTATUS; 691 break; 692 case MII_PHYSID1: 693 data = KSZ8795_ID_HI; 694 break; 695 case MII_PHYSID2: 696 if (ksz_is_ksz88x3(dev)) 697 data = KSZ8863_ID_LO; 698 else 699 data = KSZ8795_ID_LO; 700 break; 701 case MII_ADVERTISE: 702 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 703 data = ADVERTISE_CSMA; 704 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 705 data |= ADVERTISE_PAUSE_CAP; 706 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 707 data |= ADVERTISE_100FULL; 708 if (ctrl & PORT_AUTO_NEG_100BTX) 709 data |= ADVERTISE_100HALF; 710 if (ctrl & PORT_AUTO_NEG_10BT_FD) 711 data |= ADVERTISE_10FULL; 712 if (ctrl & PORT_AUTO_NEG_10BT) 713 data |= ADVERTISE_10HALF; 714 break; 715 case MII_LPA: 716 ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 717 data = LPA_SLCT; 718 if (link & PORT_REMOTE_SYM_PAUSE) 719 data |= LPA_PAUSE_CAP; 720 if (link & PORT_REMOTE_100BTX_FD) 721 data |= LPA_100FULL; 722 if (link & PORT_REMOTE_100BTX) 723 data |= LPA_100HALF; 724 if (link & PORT_REMOTE_10BT_FD) 725 data |= LPA_10FULL; 726 if (link & PORT_REMOTE_10BT) 727 data |= LPA_10HALF; 728 if (data & ~LPA_SLCT) 729 data |= LPA_LPACK; 730 break; 731 case PHY_REG_LINK_MD: 732 ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 733 ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 734 if (val1 & PORT_START_CABLE_DIAG) 735 data |= PHY_START_CABLE_DIAG; 736 737 if (val1 & PORT_CABLE_10M_SHORT) 738 data |= PHY_CABLE_10M_SHORT; 739 740 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 741 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 742 743 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 744 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 745 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 746 break; 747 case PHY_REG_PHY_CTRL: 748 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 749 if (link & PORT_MDIX_STATUS) 750 data |= KSZ886X_CTRL_MDIX_STAT; 751 break; 752 default: 753 processed = false; 754 break; 755 } 756 if (processed) 757 *val = data; 758 } 759 760 void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 761 { 762 u8 restart, speed, ctrl, data; 763 const u8 *regs; 764 u8 p = phy; 765 766 regs = dev->info->regs; 767 768 switch (reg) { 769 case MII_BMCR: 770 771 /* Do not support PHY reset function. */ 772 if (val & BMCR_RESET) 773 break; 774 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 775 data = speed; 776 if (val & KSZ886X_BMCR_HP_MDIX) 777 data |= PORT_HP_MDIX; 778 else 779 data &= ~PORT_HP_MDIX; 780 if (data != speed) 781 ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data); 782 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 783 data = ctrl; 784 if (ksz_is_ksz88x3(dev)) { 785 if ((val & BMCR_ANENABLE)) 786 data |= PORT_AUTO_NEG_ENABLE; 787 else 788 data &= ~PORT_AUTO_NEG_ENABLE; 789 } else { 790 if (!(val & BMCR_ANENABLE)) 791 data |= PORT_AUTO_NEG_DISABLE; 792 else 793 data &= ~PORT_AUTO_NEG_DISABLE; 794 795 /* Fiber port does not support auto-negotiation. */ 796 if (dev->ports[p].fiber) 797 data |= PORT_AUTO_NEG_DISABLE; 798 } 799 800 if (val & BMCR_SPEED100) 801 data |= PORT_FORCE_100_MBIT; 802 else 803 data &= ~PORT_FORCE_100_MBIT; 804 if (val & BMCR_FULLDPLX) 805 data |= PORT_FORCE_FULL_DUPLEX; 806 else 807 data &= ~PORT_FORCE_FULL_DUPLEX; 808 if (data != ctrl) 809 ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data); 810 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 811 data = restart; 812 if (val & KSZ886X_BMCR_DISABLE_LED) 813 data |= PORT_LED_OFF; 814 else 815 data &= ~PORT_LED_OFF; 816 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 817 data |= PORT_TX_DISABLE; 818 else 819 data &= ~PORT_TX_DISABLE; 820 if (val & BMCR_ANRESTART) 821 data |= PORT_AUTO_NEG_RESTART; 822 else 823 data &= ~(PORT_AUTO_NEG_RESTART); 824 if (val & BMCR_PDOWN) 825 data |= PORT_POWER_DOWN; 826 else 827 data &= ~PORT_POWER_DOWN; 828 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 829 data |= PORT_AUTO_MDIX_DISABLE; 830 else 831 data &= ~PORT_AUTO_MDIX_DISABLE; 832 if (val & KSZ886X_BMCR_FORCE_MDI) 833 data |= PORT_FORCE_MDIX; 834 else 835 data &= ~PORT_FORCE_MDIX; 836 if (val & BMCR_LOOPBACK) 837 data |= PORT_PHY_LOOPBACK; 838 else 839 data &= ~PORT_PHY_LOOPBACK; 840 if (data != restart) 841 ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], data); 842 break; 843 case MII_ADVERTISE: 844 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 845 data = ctrl; 846 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 847 PORT_AUTO_NEG_100BTX_FD | 848 PORT_AUTO_NEG_100BTX | 849 PORT_AUTO_NEG_10BT_FD | 850 PORT_AUTO_NEG_10BT); 851 if (val & ADVERTISE_PAUSE_CAP) 852 data |= PORT_AUTO_NEG_SYM_PAUSE; 853 if (val & ADVERTISE_100FULL) 854 data |= PORT_AUTO_NEG_100BTX_FD; 855 if (val & ADVERTISE_100HALF) 856 data |= PORT_AUTO_NEG_100BTX; 857 if (val & ADVERTISE_10FULL) 858 data |= PORT_AUTO_NEG_10BT_FD; 859 if (val & ADVERTISE_10HALF) 860 data |= PORT_AUTO_NEG_10BT; 861 if (data != ctrl) 862 ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 863 break; 864 case PHY_REG_LINK_MD: 865 if (val & PHY_START_CABLE_DIAG) 866 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 867 break; 868 default: 869 break; 870 } 871 } 872 873 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 874 { 875 u8 data; 876 877 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 878 data &= ~PORT_VLAN_MEMBERSHIP; 879 data |= (member & dev->port_mask); 880 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data); 881 } 882 883 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port) 884 { 885 u8 learn[DSA_MAX_PORTS]; 886 int first, index, cnt; 887 struct ksz_port *p; 888 889 if ((uint)port < dev->info->port_cnt) { 890 first = port; 891 cnt = port + 1; 892 } else { 893 /* Flush all ports. */ 894 first = 0; 895 cnt = dev->info->port_cnt; 896 } 897 for (index = first; index < cnt; index++) { 898 p = &dev->ports[index]; 899 if (!p->on) 900 continue; 901 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]); 902 if (!(learn[index] & PORT_LEARN_DISABLE)) 903 ksz_pwrite8(dev, index, P_STP_CTRL, 904 learn[index] | PORT_LEARN_DISABLE); 905 } 906 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 907 for (index = first; index < cnt; index++) { 908 p = &dev->ports[index]; 909 if (!p->on) 910 continue; 911 if (!(learn[index] & PORT_LEARN_DISABLE)) 912 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]); 913 } 914 } 915 916 int ksz8_fdb_dump(struct ksz_device *dev, int port, 917 dsa_fdb_dump_cb_t *cb, void *data) 918 { 919 int ret = 0; 920 u16 i = 0; 921 u16 entries = 0; 922 u8 timestamp = 0; 923 u8 fid; 924 u8 member; 925 struct alu_struct alu; 926 927 do { 928 alu.is_static = false; 929 ret = ksz8_r_dyn_mac_table(dev, i, alu.mac, &fid, &member, 930 ×tamp, &entries); 931 if (!ret && (member & BIT(port))) { 932 ret = cb(alu.mac, alu.fid, alu.is_static, data); 933 if (ret) 934 break; 935 } 936 i++; 937 } while (i < entries); 938 if (i >= entries) 939 ret = 0; 940 941 return ret; 942 } 943 944 int ksz8_mdb_add(struct ksz_device *dev, int port, 945 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 946 { 947 struct alu_struct alu; 948 int index; 949 int empty = 0; 950 951 alu.port_forward = 0; 952 for (index = 0; index < dev->info->num_statics; index++) { 953 if (!ksz8_r_sta_mac_table(dev, index, &alu)) { 954 /* Found one already in static MAC table. */ 955 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 956 alu.fid == mdb->vid) 957 break; 958 /* Remember the first empty entry. */ 959 } else if (!empty) { 960 empty = index + 1; 961 } 962 } 963 964 /* no available entry */ 965 if (index == dev->info->num_statics && !empty) 966 return -ENOSPC; 967 968 /* add entry */ 969 if (index == dev->info->num_statics) { 970 index = empty - 1; 971 memset(&alu, 0, sizeof(alu)); 972 memcpy(alu.mac, mdb->addr, ETH_ALEN); 973 alu.is_static = true; 974 } 975 alu.port_forward |= BIT(port); 976 if (mdb->vid) { 977 alu.is_use_fid = true; 978 979 /* Need a way to map VID to FID. */ 980 alu.fid = mdb->vid; 981 } 982 ksz8_w_sta_mac_table(dev, index, &alu); 983 984 return 0; 985 } 986 987 int ksz8_mdb_del(struct ksz_device *dev, int port, 988 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 989 { 990 struct alu_struct alu; 991 int index; 992 993 for (index = 0; index < dev->info->num_statics; index++) { 994 if (!ksz8_r_sta_mac_table(dev, index, &alu)) { 995 /* Found one already in static MAC table. */ 996 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 997 alu.fid == mdb->vid) 998 break; 999 } 1000 } 1001 1002 /* no available entry */ 1003 if (index == dev->info->num_statics) 1004 goto exit; 1005 1006 /* clear port */ 1007 alu.port_forward &= ~BIT(port); 1008 if (!alu.port_forward) 1009 alu.is_static = false; 1010 ksz8_w_sta_mac_table(dev, index, &alu); 1011 1012 exit: 1013 return 0; 1014 } 1015 1016 int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag, 1017 struct netlink_ext_ack *extack) 1018 { 1019 if (ksz_is_ksz88x3(dev)) 1020 return -ENOTSUPP; 1021 1022 /* Discard packets with VID not enabled on the switch */ 1023 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 1024 1025 /* Discard packets with VID not enabled on the ingress port */ 1026 for (port = 0; port < dev->phy_port_cnt; ++port) 1027 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 1028 flag); 1029 1030 return 0; 1031 } 1032 1033 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 1034 { 1035 if (ksz_is_ksz88x3(dev)) { 1036 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID, 1037 0x03 << (4 - 2 * port), state); 1038 } else { 1039 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 1040 } 1041 } 1042 1043 int ksz8_port_vlan_add(struct ksz_device *dev, int port, 1044 const struct switchdev_obj_port_vlan *vlan, 1045 struct netlink_ext_ack *extack) 1046 { 1047 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1048 struct ksz_port *p = &dev->ports[port]; 1049 u16 data, new_pvid = 0; 1050 u8 fid, member, valid; 1051 1052 if (ksz_is_ksz88x3(dev)) 1053 return -ENOTSUPP; 1054 1055 /* If a VLAN is added with untagged flag different from the 1056 * port's Remove Tag flag, we need to change the latter. 1057 * Ignore VID 0, which is always untagged. 1058 * Ignore CPU port, which will always be tagged. 1059 */ 1060 if (untagged != p->remove_tag && vlan->vid != 0 && 1061 port != dev->cpu_port) { 1062 unsigned int vid; 1063 1064 /* Reject attempts to add a VLAN that requires the 1065 * Remove Tag flag to be changed, unless there are no 1066 * other VLANs currently configured. 1067 */ 1068 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 1069 /* Skip the VID we are going to add or reconfigure */ 1070 if (vid == vlan->vid) 1071 continue; 1072 1073 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1074 &fid, &member, &valid); 1075 if (valid && (member & BIT(port))) 1076 return -EINVAL; 1077 } 1078 1079 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1080 p->remove_tag = untagged; 1081 } 1082 1083 ksz8_r_vlan_table(dev, vlan->vid, &data); 1084 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1085 1086 /* First time to setup the VLAN entry. */ 1087 if (!valid) { 1088 /* Need to find a way to map VID to FID. */ 1089 fid = 1; 1090 valid = 1; 1091 } 1092 member |= BIT(port); 1093 1094 ksz8_to_vlan(dev, fid, member, valid, &data); 1095 ksz8_w_vlan_table(dev, vlan->vid, data); 1096 1097 /* change PVID */ 1098 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1099 new_pvid = vlan->vid; 1100 1101 if (new_pvid) { 1102 u16 vid; 1103 1104 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1105 vid &= ~VLAN_VID_MASK; 1106 vid |= new_pvid; 1107 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1108 1109 ksz8_port_enable_pvid(dev, port, true); 1110 } 1111 1112 return 0; 1113 } 1114 1115 int ksz8_port_vlan_del(struct ksz_device *dev, int port, 1116 const struct switchdev_obj_port_vlan *vlan) 1117 { 1118 u16 data, pvid; 1119 u8 fid, member, valid; 1120 1121 if (ksz_is_ksz88x3(dev)) 1122 return -ENOTSUPP; 1123 1124 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1125 pvid = pvid & 0xFFF; 1126 1127 ksz8_r_vlan_table(dev, vlan->vid, &data); 1128 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1129 1130 member &= ~BIT(port); 1131 1132 /* Invalidate the entry if no more member. */ 1133 if (!member) { 1134 fid = 0; 1135 valid = 0; 1136 } 1137 1138 ksz8_to_vlan(dev, fid, member, valid, &data); 1139 ksz8_w_vlan_table(dev, vlan->vid, data); 1140 1141 if (pvid == vlan->vid) 1142 ksz8_port_enable_pvid(dev, port, false); 1143 1144 return 0; 1145 } 1146 1147 int ksz8_port_mirror_add(struct ksz_device *dev, int port, 1148 struct dsa_mall_mirror_tc_entry *mirror, 1149 bool ingress, struct netlink_ext_ack *extack) 1150 { 1151 if (ingress) { 1152 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1153 dev->mirror_rx |= BIT(port); 1154 } else { 1155 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1156 dev->mirror_tx |= BIT(port); 1157 } 1158 1159 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1160 1161 /* configure mirror port */ 1162 if (dev->mirror_rx || dev->mirror_tx) 1163 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1164 PORT_MIRROR_SNIFFER, true); 1165 1166 return 0; 1167 } 1168 1169 void ksz8_port_mirror_del(struct ksz_device *dev, int port, 1170 struct dsa_mall_mirror_tc_entry *mirror) 1171 { 1172 u8 data; 1173 1174 if (mirror->ingress) { 1175 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1176 dev->mirror_rx &= ~BIT(port); 1177 } else { 1178 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1179 dev->mirror_tx &= ~BIT(port); 1180 } 1181 1182 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1183 1184 if (!dev->mirror_rx && !dev->mirror_tx) 1185 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1186 PORT_MIRROR_SNIFFER, false); 1187 } 1188 1189 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1190 { 1191 struct ksz_port *p = &dev->ports[port]; 1192 u8 data8; 1193 1194 if (!p->interface && dev->compat_interface) { 1195 dev_warn(dev->dev, 1196 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1197 "Please update your device tree.\n", 1198 port); 1199 p->interface = dev->compat_interface; 1200 } 1201 1202 /* Configure MII interface for proper network communication. */ 1203 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8); 1204 data8 &= ~PORT_INTERFACE_TYPE; 1205 data8 &= ~PORT_GMII_1GPS_MODE; 1206 switch (p->interface) { 1207 case PHY_INTERFACE_MODE_MII: 1208 p->phydev.speed = SPEED_100; 1209 break; 1210 case PHY_INTERFACE_MODE_RMII: 1211 data8 |= PORT_INTERFACE_RMII; 1212 p->phydev.speed = SPEED_100; 1213 break; 1214 case PHY_INTERFACE_MODE_GMII: 1215 data8 |= PORT_GMII_1GPS_MODE; 1216 data8 |= PORT_INTERFACE_GMII; 1217 p->phydev.speed = SPEED_1000; 1218 break; 1219 default: 1220 data8 &= ~PORT_RGMII_ID_IN_ENABLE; 1221 data8 &= ~PORT_RGMII_ID_OUT_ENABLE; 1222 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1223 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1224 data8 |= PORT_RGMII_ID_IN_ENABLE; 1225 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1226 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1227 data8 |= PORT_RGMII_ID_OUT_ENABLE; 1228 data8 |= PORT_GMII_1GPS_MODE; 1229 data8 |= PORT_INTERFACE_RGMII; 1230 p->phydev.speed = SPEED_1000; 1231 break; 1232 } 1233 ksz_write8(dev, REG_PORT_5_CTRL_6, data8); 1234 p->phydev.duplex = 1; 1235 } 1236 1237 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1238 { 1239 struct dsa_switch *ds = dev->ds; 1240 struct ksz8 *ksz8 = dev->priv; 1241 const u32 *masks; 1242 u8 member; 1243 1244 masks = ksz8->masks; 1245 1246 /* enable broadcast storm limit */ 1247 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1248 1249 if (!ksz_is_ksz88x3(dev)) 1250 ksz8795_set_prio_queue(dev, port, 4); 1251 1252 /* disable DiffServ priority */ 1253 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false); 1254 1255 /* replace priority */ 1256 ksz_port_cfg(dev, port, P_802_1P_CTRL, 1257 masks[PORT_802_1P_REMAPPING], false); 1258 1259 /* enable 802.1p priority */ 1260 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true); 1261 1262 if (cpu_port) { 1263 if (!ksz_is_ksz88x3(dev)) 1264 ksz8795_cpu_interface_select(dev, port); 1265 1266 member = dsa_user_ports(ds); 1267 } else { 1268 member = BIT(dsa_upstream_port(ds, port)); 1269 } 1270 1271 ksz8_cfg_port_member(dev, port, member); 1272 } 1273 1274 void ksz8_config_cpu_port(struct dsa_switch *ds) 1275 { 1276 struct ksz_device *dev = ds->priv; 1277 struct ksz8 *ksz8 = dev->priv; 1278 struct ksz_port *p; 1279 const u32 *masks; 1280 const u8 *regs; 1281 u8 remote; 1282 int i; 1283 1284 masks = ksz8->masks; 1285 regs = dev->info->regs; 1286 1287 /* Switch marks the maximum frame with extra byte as oversize. */ 1288 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true); 1289 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1290 1291 p = &dev->ports[dev->cpu_port]; 1292 p->on = 1; 1293 1294 ksz8_port_setup(dev, dev->cpu_port, true); 1295 1296 for (i = 0; i < dev->phy_port_cnt; i++) { 1297 p = &dev->ports[i]; 1298 1299 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1300 1301 /* Last port may be disabled. */ 1302 if (i == dev->phy_port_cnt) 1303 break; 1304 p->on = 1; 1305 p->phy = 1; 1306 } 1307 for (i = 0; i < dev->phy_port_cnt; i++) { 1308 p = &dev->ports[i]; 1309 if (!p->on) 1310 continue; 1311 if (!ksz_is_ksz88x3(dev)) { 1312 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1313 if (remote & KSZ8_PORT_FIBER_MODE) 1314 p->fiber = 1; 1315 } 1316 if (p->fiber) 1317 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL, 1318 true); 1319 else 1320 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL, 1321 false); 1322 } 1323 } 1324 1325 static int ksz8_handle_global_errata(struct dsa_switch *ds) 1326 { 1327 struct ksz_device *dev = ds->priv; 1328 int ret = 0; 1329 1330 /* KSZ87xx Errata DS80000687C. 1331 * Module 2: Link drops with some EEE link partners. 1332 * An issue with the EEE next page exchange between the 1333 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 1334 * the link dropping. 1335 */ 1336 if (dev->info->ksz87xx_eee_link_erratum) 1337 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 1338 1339 return ret; 1340 } 1341 1342 int ksz8_enable_stp_addr(struct ksz_device *dev) 1343 { 1344 struct alu_struct alu; 1345 1346 /* Setup STP address for STP operation. */ 1347 memset(&alu, 0, sizeof(alu)); 1348 ether_addr_copy(alu.mac, eth_stp_addr); 1349 alu.is_static = true; 1350 alu.is_override = true; 1351 alu.port_forward = dev->info->cpu_ports; 1352 1353 ksz8_w_sta_mac_table(dev, 0, &alu); 1354 1355 return 0; 1356 } 1357 1358 int ksz8_setup(struct dsa_switch *ds) 1359 { 1360 struct ksz_device *dev = ds->priv; 1361 int i; 1362 1363 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true); 1364 1365 /* Enable automatic fast aging when link changed detected. */ 1366 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 1367 1368 /* Enable aggressive back off algorithm in half duplex mode. */ 1369 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1, 1370 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 1371 1372 /* 1373 * Make sure unicast VLAN boundary is set as default and 1374 * enable no excessive collision drop. 1375 */ 1376 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2, 1377 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 1378 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 1379 1380 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 1381 1382 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1383 1384 if (!ksz_is_ksz88x3(dev)) 1385 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 1386 1387 for (i = 0; i < (dev->info->num_vlans / 4); i++) 1388 ksz8_r_vlan_entries(dev, i); 1389 1390 return ksz8_handle_global_errata(ds); 1391 } 1392 1393 void ksz8_get_caps(struct ksz_device *dev, int port, 1394 struct phylink_config *config) 1395 { 1396 config->mac_capabilities = MAC_10 | MAC_100; 1397 1398 /* Silicon Errata Sheet (DS80000830A): 1399 * "Port 1 does not respond to received flow control PAUSE frames" 1400 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 1401 * switches. 1402 */ 1403 if (!ksz_is_ksz88x3(dev) || port) 1404 config->mac_capabilities |= MAC_SYM_PAUSE; 1405 1406 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 1407 if (!ksz_is_ksz88x3(dev)) 1408 config->mac_capabilities |= MAC_ASYM_PAUSE; 1409 } 1410 1411 u32 ksz8_get_port_addr(int port, int offset) 1412 { 1413 return PORT_CTRL_ADDR(port, offset); 1414 } 1415 1416 int ksz8_switch_init(struct ksz_device *dev) 1417 { 1418 struct ksz8 *ksz8 = dev->priv; 1419 1420 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 1421 dev->phy_port_cnt = dev->info->port_cnt - 1; 1422 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 1423 1424 if (ksz_is_ksz88x3(dev)) { 1425 ksz8->masks = ksz8863_masks; 1426 ksz8->shifts = ksz8863_shifts; 1427 } else { 1428 ksz8->masks = ksz8795_masks; 1429 ksz8->shifts = ksz8795_shifts; 1430 } 1431 1432 /* We rely on software untagging on the CPU port, so that we 1433 * can support both tagged and untagged VLANs 1434 */ 1435 dev->ds->untag_bridge_pvid = true; 1436 1437 /* VLAN filtering is partly controlled by the global VLAN 1438 * Enable flag 1439 */ 1440 dev->ds->vlan_filtering_is_global = true; 1441 1442 return 0; 1443 } 1444 1445 void ksz8_switch_exit(struct ksz_device *dev) 1446 { 1447 ksz8_reset_switch(dev); 1448 } 1449 1450 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 1451 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 1452 MODULE_LICENSE("GPL"); 1453